SC26C198 datasheet(46/49 Pages) PHILIPS

46 / 49 page

Philips Semiconductors

Product specification

SC26C198 SC68C198

SC26L198 SC68L198

Octal UART with TTL compatibility at 3.3V

and 5V supply voltages

1995 May 1

381

SCLK

IACKN

CEN

W_RN

ADDRESS

DATA

DACKN

INVALID

DON’T CARE

VALID

tCS

tRWS

tAS

tAH

tDD

DAKDLY

CEN

HIGH

tDF

INVALID

DON’T CARE

NOTE:

CEN must not be active during an IACKN cycle. If CEN is active, IACKN will be ignored

and a normal read or write will be executed according to W_RN. In the synchronous

mode, extended IACKN signal will start another IACKN. (This may not be desired, but

is allowed.)

SD00525

Figure 6. Basic IACKN Cycle, ASYNC/SYNC

C1 and C2 should be chosen according to the

crystal manufacturer’s specification.

C1 and C2 values will include any parasitic

capacitance of the wiring.

fX1

+5V

1K required for

TTL gate.

C1 = C2 = 24pF FOR CL = 20PF

3.6864MHz

3pF

4pF

50 KOHMs

150 KOHMs

26C94

NOTES:

C1 and C2 should be based on manufacturer’s specification.

X1 and X2 parasitic capacitance IS 1-2pF AND 3-5pF, respectively.

GAIN:

at 4MHz 8 to 14db; at 8MHz 2 to 6db

PHASE: at 4MHz 272

° to 276°; at 8MHz 272° to 276°

The above figures for 5V operation. Operation at 3V is to be determined.

TYPICAL CRYSTAL SPECIFICATION

FREQUENCY:

2 – 4MHZ

LOAD CAPACITANCE (CL):

12 – 32pF

TYPE OF OPERATION:

PARALLEL RESONANT, FUNDAMENTAL MODE

MUX

remainder

of circuit

÷ 2

38.4kHz CLOCK

BRG

TO I/O CHANGE-OF-STATE DETECTORS

STANDARD

BAUD

RATES

X1 L/H

T/R fX1

SD00198

Figure 7. X1/X2 Communication Crystal Clock

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