DS28EC20

Analog Devices, Inc.

18 of 28

support a standard communication speed of 16.3kbps and overdrive of 142kbps. The slightly reduced rates for the

DS28EC20 are a result of additional recovery times, which in turn were driven by a 1-Wire physical interface

enhancement to improve noise immunity. The value of the pullup resistor primarily depends on the network size

and load conditions. The DS28EC20 requires a pullup resistor of 2.2kΩ (max) at any speed.

The idle state for the 1-Wire bus is high. If for any reason a transaction needs to be suspended, the bus MUST be

left in the idle state if the transaction is to resume. If this does not occur and the bus is left low for more than 16µs

(overdrive speed) or more than 120µs (standard speed), one or more devices on the bus can be reset.

Figure 8. Hardware Configuration

Open-Drain

Port Pin

RX = RECEIVE

TX = TRANSMIT

50Ω

MOSFET

VPUP

RX

TX

TX

RX

DATA

RPUP

IL

BUS CONTROLLER

DS28EC20 1-Wire PORT

TRANSACTION SEQUENCE

The protocol for accessing the DS28EC20 through the 1-Wire port is as follows:



Initialization



ROM Function Command



Memory Function Command



Transaction/Data

INITIALIZATION

All transactions on the 1-Wire bus begin with an initialization sequence. The initialization sequence consists of a

reset pulse transmitted by the bus controller followed by presence pulse(s) transmitted by the peripheral(s). The

presence pulse lets the bus controller know that the DS28EC20 is on the bus and is ready to operate. For more

details, see the 1-Wire Signaling section.

1-Wire ROM FUNCTION COMMANDS

Once the bus controller has detected a presence, it can issue one of the seven ROM function commands that the

DS28EC20 supports. All ROM function commands are 8 bits long. See Figure 9 for list of these commands.

READ ROM [33h]

This command allows the bus controller to read the DS28EC20’s 8-bit family code, unique 48-bit serial number,

and 8-bit CRC. This command can only be used if there is a single peripheral on the bus. If more than one

peripheral is present on the bus, a data collision occurs when all peripherals try to transmit at the same time (open

drain produces a wired-AND result). The resultant family code and 48-bit serial number result in a mismatch of the

CRC.