Philips Semiconductors

Product specification

SC68C94

Quad universal asynchronous receiver/transmitter (QUART)

1995 May 1

19

Table 8.

Register Bit Formats, I/O Section

Bit 7

Bit 6

Bit 5

Bit 4

Bit 3

Bit 2

Bit 1

Bit 0

IPCR (Input Port Change Register ab) The lower four bits replicate the lower four bits of the IPR. The upper four bits reads state of

Change detectors. Change detectors are enabled in ACR[3:0]. (DUART ab)

DeltaI/O1b

Delta I/O0b

Delta I/O1a

Delta I/O0a

I/O1b

I/O0b

I/O1a

I/O0a

0 = No

1 = Yes

0 = No

1 = Yes

0 = No

1 = Yes

0 = No

1 = Yes

0 = Low

1 = High

0 = Low

1 = High

0 = Low

1 = High

0 = Low

1 = High

IPCR (Input Port Change Register cd) The lower four bits replicate the lower four bits of the IPR. The upper four bits reads state of

Change detectors. Change detectors are enabled in ACR[3:0]. (DUART cd)

Delta I/O1d

Delta I/O0d

Delta I/O1c

Delta I/O0c

I/O1d

I/O0d

I/O1c

I/O0c

0 = No

1 = Yes

0 = No

1 = Yes

0 = No

1 = Yes

0 = No

1 = Yes

0 = Low

1 = High

0 = Low

1 = High

0 = Low

1 = High

0 = Low

1 = High

I/OPCR (I/O Port Configuration Register) One register for each UART.

I/O3x CONTROL

I/O2x CONTROL

I/O1x CONTROL

I/O0x CONTROL

Two bits for each I/O pin.

This register controls the configuration of the I/O ports. It defines them as inputs or outputs and controls what sources will drive them in the

case of outputs or which functions they will drive when used as an input. Each pin has four functions and hence two bits to control it. Each

UART has one eight bit register to control its four I/O ports.

OPR (Output Port Register cd) for DUART cd

I/O3d

I/O2d

I/O3c

I/O2c

I/O1d

I/O0d

I/O1c

I/O0c

One bit for each pin. When I/O pins are configured as “General Purpose Outputs”

the pins will be driven to the complement value of its associated OPR bit.

OPR (Output Port Register ab) for DUART ab

I/O3b

I/O2b

I/O3a

I/O2a

I/O1b

I/O0b

I/O1a

I/O0a

One bit for each pin. When I/O pins are configured as “General Purpose Outputs”

the pins will be driven to the complement value of its associated OPR bit.

This register contains the data for the I/O ports when they are used as ’General Purpose Outputs’ . The bits of the register are controlled by

writing to the hex addresses at 0C and 1C. Ones written to the OPR drive the pins to 0; zeros drive the pins to 1. (The pins drive the value of

the complement data written to the OPR)

IPR (Input Port Register cd) Reads I/O pins for DUART cd

I/O3d

I/O2d

I/O3c

I/O2c

I/O1d

I/O0d

I/O1c

I/O0c

0 = Low

1 = High

0 = Low

1 = High

0 = Low

1 = High

0 = Low

1 = High

0 = Low

1 = High

0 = Low

1 = High

0 = Low

1 = High

0 = Low

1 = High

IPR (Input Port Register ab) Reads I/O pins for DUART ab

I/O3b

I/O2b

I/O3a

I/O2a

I/O1b

I/O0b

I/O1a

I/O0a

0 = Low

1 = High

0 = Low

1 = High

0 = Low

1 = High

0 = Low

1 = High

0 = Low

1 = High

0 = Low

1 = High

0 = Low

1 = High

0 = Low

1 = High

This register reads the state of the ’I/O Ports’. The state of the I/O ports is read regardless of being programmed as inputs or outputs.

The IPR can be thought of a just another 8 bit parallel port to the system data bus. The lower four bits of this register are replicated in the

lower four bits of the IPCR register.

I/O Port Control Channel A (IOPCRA)

IOPCR[xx]

Pin Control Bits

IOPCRa[7:6]

IOPCRa[5:4]

IOPCRa[3:2]

IOPCRa[1:0]

IOPCR[xx]

Pin Control Bits

I/O3A

I/O2A

I/O1A

I/O0A

00 = input

IPR(5), TxC in

IPR(4), RxC in

TxC in

IPR(0), CTSN

01 = output

OPRab(5)

OPRab(4)

01

OPRab(1)

≠

01

OPRab(0)