Data Sheet

AD5674/AD5674R/AD5679/AD5679R

Rev. B | Page 27 of 32

LOAD DAC (HARDWARE LDAC PIN)

The AD5674/AD5674R/AD5679/AD5679R DACs have double

buffered interfaces consisting of two banks of registers: input

registers and DAC registers. The user can write to any

combination of the input registers. Updates to the DAC register

are controlled by the LDAC pin.

Instantaneous DAC Updating (LDAC Held Low)

For instantaneous updating of the DACs, LDAC is held low and

data is clocked to the input register using Command 0001. Both

the addressed input register and the DAC register are updated

on the rising edge of SYNC, and the output begins to change

(see Table 17).

Figure 63. Simplified Diagram of Input Loading Circuitry for a Single DAC

Deferred DAC Updating (LDAC is Pulsed Low)

For deferred updating of the DACs, LDAC is held high and data

is clocked to the input register using Command 0001. All DAC

outputs are asynchronously updated by bringing LDAC low

after SYNC is brought high. The update now occurs on the

falling edge of LDAC.

LDAC MASK REGISTER

Command 0101 is reserved for this software LDAC function.

Address bits are ignored. Writing to the DAC, using

Command 0101, loads the 16-bit LDAC register (DB15 to DB0).

The default for each channel is 0, that is, the LDAC pin works

normally. Setting the bits to 1 forces this DAC channel to ignore

transitions on the LDAC pin, regardless of the state of the

hardware LDAC pin. This flexibility is useful in applications

where the user wants to select which channels respond to the

LDAC pin.

The LDAC register gives the user extra flexibility and control

over the hardware LDAC pin (see Table 16). Setting the LDAC

bits (DB0 to DB15) to 0 for a DAC channel means that this

channel update is controlled by the hardware LDAC pin.

Table 16. LDAC Overwrite Definition

Load LDAC Register

LDAC Bits (DB15 to DB0)

LDAC Pin

LDAC Operation

0000000000000000

1 or 0

Determined by the LDAC pin.

1111111111111111

X1

DAC channels update and override the LDAC pin. DAC channels see LDAC as 1.

Table 17. Write Commands and LDAC Pin Truth Table1

Command

Description

Hardware LDAC Pin

State

Input Register

Contents

DAC Register Contents

0001

Write to Input Register n (dependent on

LDAC)

VLOGIC

Data update

No change (no update)

GND2

Data update

Data update

0010

Update DAC Register n with contents of

Input Register n

VLOGIC

No change

Updated with input register

contents

GND

No change

Updated with input register

contents

0011

Write to and update DAC Channel n

VLOGIC

Data update

Data update

GND

Data update

Data update

1

A high to low hardware LDAC pin transition always updates the contents of the DAC register with the contents of the input register on channels that are not masked

(blocked) by the LDAC mask register.

2

When LDAC is permanently tied low, the LDAC mask bits are ignored.

SCLK

DAC

REGISTER

INTERFACE

LOGIC

AMPLIFIER

LDAC

INPUT

REGISTER

SDI

16-BIT

DAC

VOUTX

VREF

1

X means don’t care.