AD5675R datasheet(28/32 Pages) AD

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AD5674/AD5674R/AD5679/AD5679R

Data Sheet

Rev. B | Page 28 of 32

HARDWARE RESET (RESET)

The RESET pin is an active low reset that allows the outputs to

be cleared to zero scale or midscale. The clear code value

depends on the model in use and refers to the power-up voltage.

It is necessary to keep the RESET pin low for a minimum time

(see Table 5) to complete the operation. When the RESET signal

is returned high, the output remains at the cleared value until a

new value is programmed. When the RESET pin is low, the

outputs cannot be updated with a new value. Any events on the

LDAC pin or RESET pin during power-on reset are ignored. If

the RESET pin is pulled low at power-up, the device does not

initialize properly until the pin is released.

POWER-ON RESET INTERNAL CIRCUIT

The AD5674/AD5674R/AD5679/AD5679R contain a power-on

reset circuit that controls the output voltage during power-up.

Depending on the model selected, the output powers up to zero

scale (AD5679R-1, AD5674R-1) or the output powers up to

midscale (AD5679R-2, AD5674R-2). The output remains

powered up at this level until a valid write sequence is made to

the DAC.

SOFTWARE RESET

A software executable reset function is also available that resets

the DAC to the power-on reset code. Command 0110 is

designated for this software reset function. The DAC address

bits must be set to 0x0 and the data bits set to 0x1234 for the

software reset command to execute.

INTERNAL REFERENCE SETUP

The on-chip reference is on at power-up by default. To reduce

the supply current, turn off this reference by setting the software

programmable bit, DB0, in the control register. Table 18 shows

how the state of the bit corresponds to the mode of operation.

Command 0111 is reserved for setting up the internal reference

(see Table 10 and Table 19).

Table 18. Internal Reference Setup Register

Bit

Description

DB2

Reserved

DB0

Reference enable

DB0 = 0: internal reference enabled (default)

DB0 = 1: internal reference disabled

Table 19. 24-Bit Input Shift Register Contents for Internal Reference Setup Command

DB23 (MSB)

DB22

DB21

DB20

DB19 to DB3

DB2

DB1

DB0 (LSB)

Don’t care

Reserved

Reserved, set to 0

Reference enable

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