Detailed Description

The DS28C16 integrates the Maxim DeepCover® capability to protect all device stored data from invasive discovery. In

addition to the SHA-3 engine for signatures, 256-bit EEPROM for user memory, SHA-3 secret storage, 17-bit decrement

counter, and control registers. The device operates from an I2C interface.

I2C FUNCTION

CONTROL

AND

COMMAND

64-BIT ROM ID

BUFFER

E2 ARRAY

SHA3-256

DS28C16

DS28C16

USER MEMORY

DECREMENT COUNTER

SECRET

VCC

SDA

SCL

Figure 1. Block Diagram

Design Resource Overview

Operation of the DS28C16 involves use of device EEPROM and execution of device function commands. The following

section provides an overview including the decrement counter. Refer to the DS28C16 Security User Guide for details.

Memory

A secured EEPROM array provides SHA-3 secret storage, along with a decrement counter, and/or general-purpose,

user-programmable memory. Depending on the memory space, there are either default or user-programmable options to

set protection modes.

Decrement Counter

The optional 17-bit decrement counter can be written one time on a page of memory. A dedicated device function

command is used to decrement the count value by one with each call. Once the count value reaches a value of 0, no

additional decrements are possible.

I2C

General Characteristics

The I2C bus uses a data line (SDA) plus a clock signal (SCL) for communication. Both SDA and SCL are bidirectional

lines, connected to a positive supply voltage through a pullup resistor. When there is no communication, both lines are

high. The output stages of devices connected to the bus must have an open drain or open collector to perform the wired-

AND function. Data on the I2C bus can be transferred at rates up to 100kbps in standard mode and up to 400kbps in

DS28C16

I2C Low-Voltage SHA-3 Authenticator

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