START Condition

To initiate communication with a slave, the master must generate a START condition. A START condition is defined as a

change in state of SDA from high to low while SCL remains high.

STOP Condition

To end communication with a slave, the master must generate a STOP condition. A STOP condition is defined as a

change in state of SDA from low to high while SCL remains high.

Repeated START Condition

Repeated STARTs are commonly used for read accesses after having specified a memory address to read from in a

preceding write access. The master can use a repeated START condition at the end of a data transfer to immediately

initiate a new data transfer following the current one. A repeated START condition is generated the same way as a normal

START condition, but without leaving the bus idle after a STOP condition.

Data Valid

With the exception of the START and STOP condition, transitions of SDA can occur only during the low state of SCL.

The data on SDA must remain valid and unchanged during the entire high pulse of SCL plus the required setup and hold

time (tHD:DAT after the falling edge of SCL and tSU:DAT before the rising edge of SCL; see Figure 4). There is one clock

pulse per bit of data. Data is shifted into the receiving device during the rising edge of the SCL pulse.

When finished with writing, the master must release the SDA line for a sufficient amount of setup time (minimum tSU:DAT,

+ tR in Figure 4) before the next rising edge of SCL to start reading. The slave shifts out each data bit on SDA at the

falling edge of the previous SCL pulse and the data bit is valid at the rising edge of the current SCL pulse. The master

generates all SCL clock pulses, including those needed to read from a slave.

tHD:STA

tBUF

SDA

SCL

NOTE:

NOTE: TIMING REFERENCED TO VIH(MIN) AND VIL(MAX).

tF

tR

tLOW

tHD:DAT

tHIGH

tSU:DAT

tSU:STA

tSU:STO

S

Sr

P

S

tSP

tF/tOF

tF IF MASTER DRIVEN OR tOF IF SLAVE DRIVEN

Figure 4. I2C Timing Diagram

DS28C16

I2C Low-Voltage SHA-3 Authenticator

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