fast mode. The DS28C16 works in both modes or up to a clock rate of 1MHz. A device that sends data on the bus is

defined as a transmitter, and a device receiving data is defined as a receiver. The device that controls communication is

called a master. Devices controlled by the master are slaves. To be individually accessed, each device must have a slave

address that does not conflict with other devices on the bus. Data transfers can be initiated only when the bus is not busy.

The master generates the serial clock (SCL), controls the bus access, generates the START and STOP conditions, and

determines the number of data bytes transferred between START and STOP (Figure 2). Data is transferred in bytes with

the most significant bit being transmitted first. An acknowledge bit follows each byte to allow synchronization between

master and slave.

Slave Address

The slave address to which the DS28C16 responds is shown in Figure 3. The slave address is part of the slave address/

control byte. The last bit of the slave address/control byte (R/W) defines the data direction. When set to 0, subsequent

data flows from master to slave (write access); when set to 1, data flows from slave to master (read access).

SDA

SCL

S

1-7

MSB FIRST

SLAVE

ADDRESS

R/W

8

9

ACK

MSB

1-7

8

9

LSB

ACK

DATA

MSB

1-7

8

LSB

DATA

REPEATED IF MORE BYTES

ARE TRANSFERRED

9

ACK/

NACK

P

IDLE

Figure 2. I2C Protocol Overview

0

A6

0

A5

1

A4

1

A3

0

A2

0

A1

1

A0

R/W

MSB

7-BIT SLAVE ADDRESS

DETERMINES READ OR

WRITE

Figure 3. I2C Slave Address

I2C Definitions

The following terminology is commonly used to describe I2C data transfers. The timing references are defined in Figure

4.

Bus Idle or Not Busy

Both SDA and SCL are inactive and in their logic-high states.

DS28C16

I2C Low-Voltage SHA-3 Authenticator

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