LTC3417 datasheet(18/20 Pages) LINER

18 / 20 page

LTC3417

3417fb

Board Layout Considerations

When laying out the printed circuit board, the following

checklist should be used to ensure proper operation of the

LTC3417. These items are also illustrated graphically in

the layout diagram of Figure 5. Check the following in your

layout.

1. Does the capacitor CIN connect to the power VIN1

(Pin 2), VIN2 (Pin 8), and PGND2/GNDD (Pin 17) as

close as possible (DFN package)? It may be necessary

to split CIN into two capacitors. This capacitor provides

the AC current to the internal power MOSFETs and

their drivers.

2. Are the COUT1, L1 and COUT2, L2 closely connected? The

(–) plate of COUT1 returns current to PGND1, and the

(–) plate of COUT2 returns current to the PGND2/GNDD

and the (–) plate of CIN.

3. The resistor divider, R1 and R2, must be connected

between the (+) plate of COUT1 and a ground line

terminated near GNDA. The resistor divider, R3 and R4,

must be connected between the (+) plate of COUT2 and

a ground line terminated near GNDA. The feedback

signals VFB1 and VFB2 should be routed away from noise

components and traces, such as the SW lines, and its

trace should be minimized.

4. Keep sensitive components away from the SW pins.

The input capacitor CIN, the compensation capacitors

CC1, CC2, CITH1 and CITH2 and all resistors R1, R2, R3,

R4, RITH1and RITH2 should be routed away from the SW

traces and the inductors L1 and L2.

5. A ground plane is preferred, but if not available, keep the

signal and power grounds segregated with small signal

components returning to the GNDA pin at one point

which is then connected to the PGND2/GNDD pin.

6. Flood all unused areas on all layers with copper. Flood-

ing with copper will reduce the temperature rise of

power components. These copper areas should be

connected to one of the input supplies.

APPLICATIO S I FOR ATIO

VIN2

PGND2/

EXPOSED PAD

VIN1

PGND1

SW1

VFB1

ITH1

FREQ

RUN1

MODE

LTC3417

GNDD

VIN

CIN

µF

CIN2

0.1

µF

CIN1

0.1

µF

COUT2

VOUT2

COUT1

VOUT1

CC2

CC1

RITH2

CITH2

CITH1

RITH1

STAR TO

GNDA

STAR TO

GNDA

SW2

VFB2

ITH2

PGOOD

RUN2

PHASE

Figure 5

LTC3417 Datasheet(PDF) 18 Page - Linear Technology

LTC3417 Datasheet(HTML) 18 Page - Linear Technology

Html Pages

1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20

Datasheet Download

Link URL