LTC4215CUFD datasheet(14/24 Pages) LINER

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LTC4215

4215fb

APPLICATIO S I FOR ATIO

FET Short Fault

A FET short fault is reported if the data converter measures

a current sense voltage greater than or equal to 1.6mV

while the GATE is turned off. This condition sets FET short

present bit, C5, and FET short fault bit D5.

Power Bad Fault

A power bad fault is reported if the FB pin voltage drops

below its 1.235V threshold for more than 2µs when the

GATE is high. This pulls the GPIO pin low immediately

when conﬁgured as power-good, and sets power-bad

present bit, C3, and power bad fault bit D3. A circuit pre-

vents power-bad faults if the GATE-to-SOURCE voltage is

low, eliminating false power-bad faults during power-up

or power-down. If the FB pin voltage subsequently rises

back above the threshold, the GPIO pin returns to a high

impedance state and bit C3 is reset.

Fault Alerts

When any of the fault bits in FAULT register D are set, an

optional bus alert is generated if the appropriate bit in the

⎯A⎯L⎯E⎯R⎯T register B has been set. This allows only selected

faults to generate alerts. At power-up the default state is to

not alert on faults. If an alert is enabled, the correspond-

ing fault causes the

⎯A⎯L⎯E⎯R⎯T pin to pull low. After the bus

master controller broadcasts the Alert Response Address,

the LTC4215 responds with its address on the SDA line and

releases

⎯A⎯L⎯E⎯R⎯T as shown in Table 6. If there is a collision

between two LTC4215s responding with their addresses

simultaneously, then the device with the lower address

wins arbitration and responds ﬁrst. The

⎯A⎯L⎯E⎯R⎯T line is also

released if the device is addressed by the bus master.

Once the

⎯A⎯L⎯E⎯R⎯T signal has been released for one fault, it

is not pulled low again until the FAULT register indicates a

different fault has occurred or the original fault is cleared

and it occurs again. Note that this means repeated or

continuing faults do not generate alerts until the associ-

ated FAULT register bit has been cleared.

Resetting Faults

Faults are reset with any of the following conditions. First,

a serial bus command writing zeros to the FAULT register

D clears the associated faults. Second, the entire FAULT

pin or bit A3 going from high to low, if the UV pin is brought

below its 0.4V reset threshold for 2µs, or if INTVCC falls

below its 2.64V undervoltage lockout threshold. Finally,

when

⎯E⎯N is brought from high to low, only FAULT bits

D0-D3 are cleared, and bit D4, that indicates a

⎯E⎯N change

of state, is set. Note that faults that are still present, as

indicated in STATUS Register C, cannot be cleared.

The FAULT register is not cleared when auto-retrying.

When auto-retry is disabled the existence of a D0, D1

or D2 fault keeps the switch off. As soon as the fault is

cleared, the switch turns on. If auto-retry is enabled, then

a high value in C0, C1 or C2 holds the switch off and the

fault register is ignored. Subsequently, when bits C0, C1

and C2 are cleared by removal of the fault condition, the

switch is allowed to turn on again.

Data Converter

The LTC4215 incorporates an 8-bit A/D converter that con-

tinuously monitors three different voltages. The SOURCE

pin has a 1/12.5 resistive divider to monitor a full scale

voltage of 15.4V with 60mV resolution. The ADIN pin is

monitored with a 1.235V full scale and 4.82mV resolution,

and the voltage between the VDD and SENSE pins is moni-

tored with a 38.6mV full scale and 151µV resolution.

Results from each conversion are stored in registers E

(Sense), F (Source) and G (ADIN), as seen in Tables 6-8,

–

1.235V

GND

MOTHERBOARD

CONNECTOR

PLUG-IN

CARD

SOURCE

OUT

LTC4215

CEN

LOAD

4215 F04

Figure 4. Plug-In Card Insertion/Removal

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