LTC4215CUFD datasheet(16/24 Pages) LINER

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LTC4215

4215fb

APPLICATIO S I FOR ATIO

The inrush dI/dt is set to 10A/ms using CSS:

dI dt

µA

SENSE

⎛

⎝

⎞

⎠

•.

•

0 0375

10000

••.

•

0 0375

Ω

For a start-up time of 4ms with a 2x safety margin we

choose:

ms µF

TIMER

STARTUP

TIMER

12 3

•

12 3

068

.•

ms µF

µF

+≅

Note the minimum value of CTIMER is 10nF, and each 1nF

of soft-start capacitance needs 10nF of TIMER capaci-

tance/time during start-up.

Choose R1, R2, R3, R7 and R8 for the UV, OV and PG

threshold voltages:

VOV(RISING) = 14.0V, VOV(FALLING) = 13.5V (using VOV(TH)

= 1.235 rising and 1.185V falling)

VUV(RISING) = 10.75V, VUV(FALLING) = 10.6V (using VUV(TH)

= 1.235V rising and 1.215V falling)

VPG(RISING) = 11.6V, VPG(FALLING) = 10.85V (using VFB(TH)

= 1.235V rising and 1.155V falling)

A 0.1µF capacitor, CF, is placed on the UV pin to prevent

supply glitches from turning off the GATE via UV or OV.

The address is set with the help of Table 1, which indi-

cates binary address 1010011 corresponds to address

19. Address 19 is set by setting ADR2 high, ADR1 open

and ADR0 high.

Next the value of R5 and R6 are chosen to be the default

values 10Ω and 15k as discussed previously.

In addition a 0.1µF ceramic bypass capacitor is placed

on the INTVCC pin.

Layout Considerations

To achieve accurate current sensing, a Kelvin connection

is required. The minimum trace width for 1oz copper

foil is 0.02" per amp to make sure the trace stays at a

reasonable temperature. Using 0.03" per amp or wider

is recommended. Note that 1oz copper exhibits a sheet

resistance of about 530µΩ/®. Small resistances add up

quickly in high current applications. To improve noise

immunity, put the resistive dividers to the UV, OV and FB

pins close to the device and keep traces to VDD and GND

short. It is also important to put the bypass capacitor for

the INTVCC pin, C3, as close as possible between INTVCC

and GND. A 0.1µF capacitor from the UV pin (and OV pin

through resistor R2) to GND also helps reject supply noise.

Figure 4 shows a layout that addresses these issues. Note

that a surge suppressor, Z1, is placed between supply and

ground using wide traces.

GND

SDAO

GPIO

INTVCC

TIMER

ADIN

ADR2

ADR1

SENSE RESISTOR RS

LTC4215UFD

ILOAD

4215 F05

ILOAD

Figure 5. Recommended Layout

Digital Interface

The LTC4215 communicates with a bus master using a

2-wire interface compatible with I2C Bus and SMBus, an

I2C extension for low power devices.

The LTC4215 is a read-write slave device and supports

SMBus bus Read Byte, Write Byte, Read Word and Write

Word commands. The second word in a Read Word com-

mand is identical to the ﬁrst word. The second word in a

Write Word command is ignored. Data formats for these

commands are shown in Figures 6 to 11.

LTC4215CUFD Datasheet(PDF) 16 Page - Linear Technology

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