LTC4215CUFD datasheet(17/24 Pages) LINER

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LTC4215

4215fb

APPLICATIO S I FOR ATIO

START and STOP Conditions

When the bus is idle, both SCL and SDA are high. A bus

master signals the beginning of a transmission with a start

condition by transitioning SDA from high to low while SCL

is high, as shown in Figure 6. When the master has ﬁnished

communicating with the slave, it issues a STOP condition

by transitioning SDA from low to high while SCL is high.

The bus is then free for another transmission.

I2C Device Addressing

Twenty-seven distinct bus addresses are available using

three 3-state address pins, ADR0-ADR2. Table 1 shows

the correspondence between pin states and addresses.

Note that address bits B7 and B6 are internally conﬁgured

to 10. In addition, the LTC4215 responds to two special

addresses. Address (1011 111) is a mass write address

that writes to all LTC4215s, regardless of their individual

address settings. Mass write can be disabled by setting

Response Address. If the LTC4215 is pulling low on the

⎯A⎯L⎯E⎯R⎯T pin, it acknowledges this address by broadcasting

its address and releasing the

⎯A⎯L⎯E⎯R⎯T pin.

Acknowledge

The acknowledge signal is used in handshaking between

transmitter and receiver to indicate that the last byte of

data was received. The transmitter always releases the

SDA line during the acknowledge clock pulse. When the

slave is the receiver, it pulls down the SDA line so that it

remains LOW during this pulse to acknowledge receipt

of the data. If the slave fails to acknowledge by leaving

SDA high, then the master may abort the transmission by

generating a STOP condition. When the master is receiving

data from the slave, the master pulls down the SDA line

during the clock pulse to indicate receipt of the data. After

the last byte has been received the master leaves the SDA

line HIGH (not acknowledge) and issues a stop condition

to terminate the transmission.

Write Protocol

The master begins communication with a START con-

dition followed by the seven bit slave address and the

⎯W bit set to zero, as shown in Figure 7. The addressed

LTC4215 acknowledges this and then the master sends

a command byte which indicates which internal register

the master wishes to write. The LTC4215 acknowledges

this and then latches the lower three bits of the command

byte into its internal Register Address pointer. The master

then delivers the data byte and the LTC4215 acknowledges

once more and latches the data into its control register.

The transmission is ended when the master sends a STOP

condition. If the master continues sending a second data

byte, as in a Write Word command, the second data byte

is acknowledged by the LTC4215 but ignored, as shown

in Figure 8.

Read Protocol

The master begins a read operation with a START con-

dition followed by the seven bit slave address and the

⎯W bit set to zero, as shown in Figure 9. The addressed

LTC4215 acknowledges this and then the master sends

a command byte which indicates which internal register

the master wishes to read. The LTC4215 acknowledges

this and then latches the lower three bits of the command

byte into its internal Register Address pointer. The master

then sends a repeated START condition followed by the

SCL

SDA

START

CONDITION

STOP

CONDITION

ADDRESS

R/W

ACK

DATA

ACK

DATA

ACK

1 - 7

4215 F06

a6 - a0

b7 - b0

1 - 7

Figure 6. Data Transfer Over I2C or SMBus

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