LTC4215CUFD datasheet(15/24 Pages) LINER

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LTC4215

4215fb

APPLICATIO S I FOR ATIO

and are updated 10 times per second. Setting CONTROL

converter so that registers E, F, and G may be written to

and read from for software testing.

Conﬁguring the GPIO Pin

Table 2 describes the possible states of the GPIO pin using

the control register bits A6 and A7. At power-up, the default

state is for the GPIO pin to go high impedance when power

is good (FB pin greater than 1.235V). Other applications

for the GPIO pin are to pull down when power is good, a

general purpose output and a general purpose input.

Supply Transients

The LTC4215 is designed to ride through supply transients

caused by load steps. If there is a shorted load and the

parasitic inductance back to the supply is greater than

0.5µH, there is a chance that the supply collapses before

the active current limit circuit brings down the GATE pin.

If this occurs, the undervoltage monitors pull the GATE

pin low. The undervoltage lockout circuit has a 2µs ﬁlter

time after VDD drops below 2.74V. The UV pin reacts in

2µs to shut the GATE off, but it is recommended to add a

ﬁlter capacitor CF to prevent unwanted shutdown caused

by a transient. Eventually either the UV pin or undervoltage

lockout responds to bring the current under control before

the supply completely collapses.

Supply Transient Protection

The LTC4215 is safe from damage with supply voltages

up to 24V. However, spikes above 24V may damage the

part. During a short-circuit condition, large changes in

current ﬂowing through power supply traces may cause

inductive voltage spikes which exceed 24V. To minimize

such spikes, the power trace inductance should be mini-

mized by using wider traces or heavier trace plating. Also,

a snubber circuit dampens inductive voltage spikes. Build

a snubber by using a 100Ω resistor in series with a 0.1µF

capacitor between VDD and GND. A surge suppressor, Z1

in Figure 1, at the input can also prevent damage from

voltage surges.

Design Example

As a design example, take the following speciﬁcations:

VIN = 12V, IMAX = 5A, IINRUSH = 1A, dI/dtINRUSH = 10A/ms,

CL = 330µF, VUV(ON) = 10.75V, VOV(OFF) = 14.0V, VPWRGD(UP)

= 11.6V, and I2C ADDRESS = 1010011. This completed

design is shown in Figure 1.

Selection of the sense resistor, RS, is set by the overcur-

rent threshold of 25mV:

MAX

0 005

Ω

The MOSFET is sized to handle the power dissipation dur-

ing inrush when output capacitor COUT is being charged.

A method to determine power dissipation during inrush

is based on the principle that:

Energy in CL = Energy in Q1

This uses:

Energy in CL ==

()( )

033

or 0.024 joules. Calculate the time it takes to charge up

COUT:

CHARGEUP

INRUSH

•.

•

033

The power dissipated in the MOSFET:

DISS

CHARGEUP

Energy in CL

The SOA (safe operating area) curves of candidate MOS-

FETs must be evaluated to ensure that the heat capacity

of the package tolerates 6W for 4ms. The SOA curves of

the Fairchild FDC653N provide for 2A at 12V (24W) for

10ms, satisfying this requirement.

The inrush current is set to 1A using C1:

CmF

µA

or C

GATE

INRUSH

10 33

•

.•

8nF

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