AMIS-710651-A4: Color CIS Module

Data Sheet

5.0 Physical Overview

Table 2 describes a physical overview.

Table 2: Physical Overview

Parameter

Specification

Note

Image sensors

A<OS-720058

See image sensor data sheet

Module outside dimension

≅12.3mm x 18.9mm x 232mm

Figure 6

Circuit power supply

Typical 3.3V @ 70mA

Data output

One analog output

6.0 Recommended Operating Conditions

All tests were conducted at the typical pixel rate of 3.0MHz

Table 3: Recommended Operating Conditions (25

Parameter

Symbol

Min.

Typ.

Max.

Units

Power supply

VDD

3.3

V

IDD

70

100

mA

Video output level

VP

(1)

0.15

0.2

V

Reference voltage input

VREF

(2)

1.2

V

Input voltage for digital high (input clocks, SP

and CP)

VIH

3.2

VDD

VDD +0.3

V

Input voltage for digital low (input clocks SS

and CP)

VIL

0

0.8

V

Clock frequency

FREQ

(3)

0.50

3.0

4.0

MHz

Pixel frequency

PRATE

(3)

0.50

3.0

4.0

MHz

Clock pulse high duty cycle

DUTY

(4)

50

%

Clock pulse high duration

TPW

200

ns

Integration time

TINT

(5)

~1300

10000

µs

Operating temperature

TOP

(6)

25

50

Notes:

(1)

VP represents the average value Vp(n) for all n in line scans, where n is the sequential number of a pixel. This signal pixel level should be operated at less than

saturation levels, i.e., <1.3V.

(2)

VREF is used to adjust the video output bias. Under normal operation it is left unconnected.

(3)

FREQ is the input clock (CP) frequency and the pixel rate (PRATE). The minimum rate for FREQ and PRATE should be consistent with the maximum TINT, see

Note (5).

(4)

DUTY is the ratio of the clock’s pulse width to its pulse period.

(5)

TINT is the time interval between two start pulses (SP). Hence, if SP is generated from a clock count down circuit, it will be directly proportional to the clock

frequency. There must be a minimum of (56+1204) clock cycles between the two SPs. The longest integration time is determined by the degree of leakage current

degradation that can be tolerated by the system. A 10ms maximum is a typical rule-of-thumb. An experienced CIS user can use his discretion to determine the

desired leakage tolerance level for the given system.

(6)

TOP is a conservative engineering estimate. It is based on measurements of similar CIS modules. In production, they are measured under standard QA practices,

that is, under the control of ISO 9000 standards.

2

AMI Semiconductor – Aug. 06, M-20609-001

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