4

AMI Semiconductor

- Preliminary

www.amis.com

XPressArray-II 0.15m

mm Structured ASIC

Data Sheet

4.0 XPressArray-II Architecture

Figure 3 shows the XPressArray-II device architecture with

embedded block RAMs, DCI, DDR support, DLLs, PLLs, and

DCI

DCI

DCI

DCI

DLL

DLL

BRAM

BRAM

DLL

DLL

BRAM

BRAM

BRAM

PLL

Figure 3: XPressArray-II Architecture

5.0 I/O Description

The XPressArray-II I/O ring is composed of uniform I/O cell sites

and each site may be customized to support any I/O standard.

The I/O power ring is divided into eight segments, making it

compatible with the FPGA products and power supply rings built

into the packages.

I/O cells are available for a wide variety of standards as listed in

Table 3. I/O cells operate at 1.5V, 1.8V, 2.5V, and 3.3V. 3.3V

tolerant I/Os are also available. Differential signaling standards

typically require two pad sites. Signaling standards requiring a

reference voltage typically share a common reference voltage

within an I/O power ring segment, with the reference voltage

being supplied through an I/O site from an off-chip source.

Figure 4 shows the architecture of the I/O cell. Included are

programmable pull-up, pull-down resistors as well as a bus-hold

latch to limit noise on tri-stated signal busses. Dedicated dual-

data rate (DDR) flip-flops facilitate high-speed communications

with I/O operating at up to 1Gbps using LVDS transceivers in

conjunction with DLL/PLL clock management circuits.

Digital controlled impedance is available on many I/O standards

to eliminate off-chip termination resistors. Figure 5 illustrates the

termination schemes available on all XPressArray-II I/O cells.

Designers can use the DDR and DCI features of the

XPressArray-II I/O cell for DDR SDRAM memory and parallel

high-speed point-to-point interfaces.

support for a full compliment of I/O standards.

PLL

I/Os

I/Os

I/Os

I/Os

DDR

DDR