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X2P528 Datasheet(PDF) 5 Page - AMI SEMICONDUCTOR |
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X2P528 Datasheet(HTML) 5 Page - AMI SEMICONDUCTOR |
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5 / 14 page ![]() 5 AMI Semiconductor - Preliminary www.amis.com XPressArray-II 0.15m mm Structured ASIC Data Sheet I/O Standard VCCO VCCAUX Output Termination Input Termination Performance Notes LVTTL 3.3V DCI Series Out 25 W/50W 125MHz 2-24mA LVCMOS33 3.3V DCI Series Out 25 W/50W 125MHz 2-24mA LVCMOS25 2.5V DCI Series Out 25 W/50W 125MHz 2-24mA, 3.3V Tolerant LVCMOS18 1.8V DCI Series Out 25 W/50W 125MHz 2-16mA, 3.3V Tolerant LVCMOS15 1.5V DCI Series Out 25 W/50W 125MHz 2-16mA, 3.3V Tolerant PCI33_3 3.3V 33MHz PCI66 3.3V 66MHz PCI-X 133 3.3V 133MHz PCI-X 2.0 Mode 1 3.3V 133MHz PCI-X 2.0 Mode 2 1.5V 3.3V DCI Split Parallel in 114 W 266/533Mbps GTL N/A DCI Parallel Out 50 W 100MHz GTL+ N/A DCI Parallel Out 50 W 200MHz SSTL2 Class I 2.5V DCI Parallel Out 25 W DCI Split Parallel in 100 W 400Mbps SSTL2 Class II 2.5V DCI Parallel Out 25 W DCI Split Parallel in 100 W 400Mbps HSTL18 Class I 1.8V DCI Split Parallel in 100 W 500Mbps HSTL18 Class II 1.8V DCI Split Parallel in 100 W 500Mbps HSTL18 Class III 1.8V DCI Parallel in 50 W 500Mbps HSTL18 Class IV 1.8V 3.3V DCI Parallel in 50 W 500Mbps HSTL15 Class I 1.5V DCI Split Parallel in 100 W 500Mbps HSTL15 Class II 1.5V DCI Split Parallel in 100 W 500Mbps HSTL15 Class III 1.5V DCI Parallel in 50 W 500Mbps HSTL15 Class IV 1.5V 3.3V DCI Parallel in 50 W 500Mbps LVPECL (input) 3.3V 100 W Differential Input 1Gbps LVDS33 3.3V 100 W Differential Input 1Gbps LVDS25 2.5V 100 W Differential Input 1Gbps Table 3: Supported I/O Standards Figure 4: Dual Data Rate (DDR) I/O Architecture DCI Latch OEN OUT PAD VREF DCI_CNTL IN_DLY VCC GND Bus Hold ESD PullUp PullDn Register Register 0 1 MUX IN Register Register Input DDR Block Register Register 0 1 MUX OEN DDR Block Output DDR Block DCI Latch OEN OUT PAD VREF DCI_CNTL IN_DLY VCC GND Bus Hold ESD PullUp PullDn Register Register 0 1 MUX IN Register Register Input DDR Block Register Register 0 1 MUX OEN DDR Block Output DDR Block |
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