12

AMI Semiconductor

- Preliminary

www.amis.com

XPressArray-II 0.15m

mm Structured ASIC

Data Sheet

Table 9: DLL Specifications

Parameter

Value

Operating Modes

• Clock Tree

• Zero Delay Buffer

• External Feedback

• Quadrature Shift

• Basic Frequency Shift

Low/High Frequency Operation

Combined

Control Inputs

DCC (Duty Cycle Correction), TIMELOCK

Available Outputs

CLK90, CLK180, CLK270, CLK360,

CLKDV, CLK2X, LOCK, VALIDCLK

Frequency Range

25-300MHz

Clock Doubler Frequency Range

50-500MHz

Clock Divider Range

1.6-16 in 0.5 steps, 16-32 in 1.0 steps

Duty Cycle Correction Resolution

45-55%

Fine Quadrature Phase Shift Range

+/- 64 taps (@ Typical 1 Tap = 70ps)

Clock Tree Delay Compensation

Yes

Output Clock Jitter CLKO (Peak-to-Peak)

+/- 175ps

Output Clock Jitter CLK90, CLK180, CLK270 (Peak-to-Peak)

+/- 250ps

Output Clock Jitter CLK2X (Peak-to-Peak)

+/- 325ps

Output Clock Jitter CLKDV (Integer Division, Peak-to-Peak)

+/- 250ps

Output Clock Jitter CLKDV (Non-integer Division, Peak-to-Peak)

+/- 400ps

Output Clock Phase Offset (Between all Quadratures)

+/- 250ps

Lock Time

180us @ 20MHz

40us @ >60MHz

Table 10: PLL Specifications

Parameter

General Purpose Mode

LVDS Mode

Operating Modes

• Normal with Phase Shift

• LVDS

• Zero Delay Buffer

• External Feedback

• Clock Tree

Input Frequency Range

1.5-620MHz

1.5-620MHz

Input Duty Cycle

40-60%

40-60%

Input Jitter (Peak-to-Peak)

2% of input period

2% of input period

PFD Frequency Range

1-50MHz

1-50MHz

VCO Frequency Range

200-500MHz

200-1000MHz

Output Frequency Range

1-500MHz

1-800MHz

Output Duty Cycle

45-55%

45-55%

Output Period Jitter (Peak-to-Peak) 200ps

175ps

Reference Divider

1-2049

1-2049

Feedback Divider

1-2049

1-33

Post Dividers

1-2049

N/A

Phase Shift Resolution

Phase Shift Range

0-360°

0-360°

Available Outputs

FOUTA, FOUTB

FOUT90, FOUT180, FOUT270, FOUT360

Electrical specifications subject to change without notice.