7

AMI Semiconductor

- Preliminary

www.amis.com

XPressArray-II 0.15m

mm Structured ASIC

Data Sheet

Table 4: Block RAM Configurations

Port A

Port B

Name

Depth

Data

Width

Parity

Width

Depth

Width

Parity

Width

ra16_1_1_c

16,384

1

N/A

16,384

1

N/A

ra16_1_2_c

16,384

1

N/A

8,192

2

N/A

ra16_1_4_c

16,384

1

N/A

4,096

4

N/A

ra16_1_9_c

16,384

1

N/A

2,048

8

1

ra16_1_18_c

16,384

1

N/A

1,024

16

2

ra16_1_36_c

16,384

1

N/A

512

32

4

ra16_2_2_c

8,192

2

N/A

8,192

2

N/A

ra16_2_4_c

8,192

2

N/A

4,096

4

N/A

ra16_2_9_c

8,192

2

N/A

2,048

8

1

ra16_2_18_c

8,192

2

N/A

1,024

16

2

ra16_2_36_c

8,192

2

N/A

512

32

4

ra16_4_4_c

4,096

4

N/A

4,096

4

N/A

ra16_4_9_c

4,096

4

N/A

2,048

8

1

ra16_4_18_c

4,096

4

N/A

1,024

16

2

ra16_4_36_c

4,096

4

N/A

512

32

4

ra16_9_9_c

2,048

8

1

2,048

8

1

ra16_9_18_c

2,048

8

1

1,024

16

2

ra16_9_36_c

2,048

8

1

512

32

4

ra16_18_18_c

1,024

16

2

2,048

8

2

ra16_18_36_c

1,024

16

2

1,024

16

4

ra16_36_36_c

512

32

4

512

32

4

Table 5: Predefined Distributed RAMs

Name

Depth

Width

xram16x1pc

16

1

xram16x2pc

16

2

xram16x4pc

16

4

xram16x8pc

16

8

xram16x10pc

16

10

xram16x16pc

16

16

xram16x18pc

16

18

xram16x32pc

16

32

xram32x1pc

32

1

xram32x2pc

32

2

xram32x4pc

32

4

xram32x8pc

32

8

xram32x10pc

32

10

xram32x16pc

32

16

xram32x18pc

32

18

xram32x32pc

32

32

XPressArray-II devices employ clock tree synthesis, enabling

an unlimited number of clock and reset signals to be routed.

Synthesized clock trees deliver high speed clock signals with

minimal skew and power.

The XPressArray-II DLL (Figure 6) is an all digital clock

management function embedded into the XPressArray-II

bases. DLLs may be used to minimize clock insertion delay,

perform basic clock frequency synthesis and generate phase

shifts. The DLL provides both coarse and fine-grained phase

shifting with dynamic phase shift control. The quadrature clock

generation features deliver accurate clock phases at the load,

compensating for clock tree delays across the full range of

temperature and voltage. In clock divider and clock doubling

applications, duty cycle correction is available. A robust real-

time lock detection circuit completes the DLL.

7.0 Delay-Locked Loop (DLL) Description

Figure 6: DLL

CLK360

FB360

CLK270

FB270

CLK180

FB180

CLK90

FB90

CLKDV

CLK2X

CLKREF

DLL

Delay Line

PD

Control

Clk Tree

Clk Tree

Clk Tree

Clk Tree