AD5941 datasheet(65/143 Pages) AD

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Data Sheet

AD5940/AD5941

HIGH PERFORMANCE ADC CIRCUIT

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Rev. D | 65 of 143

Table 54. ADC Calibration Registers Summary (Continued)

Address

Name

Description

Reset

Access

0x00002238

ADCGAINTEMPSENS

ADC gain calibration temperature sensor channel register

0x00004000

R/W

Calibration Data Lock Register—CALDATLOCK

Address 0x00002230, Reset: 0x00000000, Name: CALDATLOCK

Table 55. Bit Descriptions for CALDATLOCK Register

Bits

Bit Name

Settings

Description

Reset

Access

[31:0]

Key

Password for calibration data registers. These bits prevent the overwriting of data after the

calibration phase.

0x0

R/W

0xDE87A5AF Write this value to unlock the calibration registers.

ADC Offset Calibration on the Low Power TIA Channel Register—ADCOFFSETLPTIA

Address 0x00002288, Reset: 0x00000000, Name: ADCOFFSETLPTIA

Table 56. Bit descriptions for ADCOFFSETLPTIA Register

Bits

Bit Name

Settings

Description

Reset

Access

[31:15]

Reserved

Reserved.

0x0

[14:0]

Value

Offset calibration for the low power TIA. The ADC offset correction for the low power TIA channel is

represented as a twos complement number. The calibration resolution is 0.25 LSBs of the ADCDAT

LSB size.

0x0

R/W

0x3FFF 4095.75. Maximum positive offset calibration value.

0x0001 0.25. Minimum positive offset calibration value.

0x0000 0. No offset adjustment.

0x7FFF −0.25. Minimum negative offset calibration value.

0x4000 −4096.0. Maximum negative offset calibration value.

ADC Gain Calibration for the Low Power TIA Channel Register—ADCGNLPTIA

Address 0x0000228C, Reset: 0x00004000, Name: ADCGNLPTIA

Table 57. Bit Descriptions for ADCGNLPTIA Register

Bits

Bit Name

Settings

Description

Reset

Access

[31:15]

Reserved

Reserved.

0x0

[14:0]

Value

Gain error calibration for the low power TIA.

0x4000

R/W

0x7FFF 2. Maximum positive gain adjustment.

0x4001 1.000 061. Minimum positive gain adjustment.

0x4000 1.0. ADC result multiplied by 1. No gain adjustment (default).

0x3FFF 0.999939. Minimum negative gain adjustment.

0x2000 0.5. ADC result multiplied by 0.5.

0x0001 0.000061. Maximum negative gain adjustment.

0x0000 0. Illegal value; results in an ADC result of 0.

ADC Offset Calibration on the High Speed TIA Channel Register—ADCOFFSETHSTIA

Address 0x00002234, Reset: 0x00000000, Name: ADCOFFSETHSTIA

AD5941 Datasheet(PDF) 65 Page - Analog Devices

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