AD5941 datasheet(16/143 Pages) AD

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Data Sheet

AD5940/AD5941

SPECIFICATIONS

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Rev. D | 16 of 143

Table 1. (Continued)

Parameter

Symbol

Min

Typ

Max

Unit

Test Conditions/Comments

START-UP TIME

Processor clock = 16 MHz

AFE Wake-Up2

Wake-up time to allow communication on SPI bus

ADC Wake-Up2

180

µs

Time delay required on exiting hibernate mode before

starting ADC conversions

1 VBIAS_CAP is only meant for internal biasing within the IC.

2 Guaranteed by design, not production tested.

3 Code distribution can be reduced if ADC output rate is reduced by using sinc2 filter option.

4 ADC offset and gain not calibrated for high power mode in production. User calibration can eliminate this error.

5 There is a correction factor of 1.835 V introduced to the ADC code to voltage conversion as a result of the calibration to the ADC.

6 A 1.835 V/1.82 V factor must be added while performing the calibration.

7 The 1.82 V reference is used to calibrate the ADC offset and gain.

8 If the ADC is calibrated and there is a hardware reset, the calibration registers are cleared to the default value. One way around this clear is to store the calibrated values in

the MCU flash during factory calibration and load those values on power-up.

9 Noise can be reduced if ADC sample rate is reduced using the sinc2 filter. See Table 2 for ADC rms noise: digital filter settings.

10 The low power TIA gain resistor must be calibrated regularly because the resistor has a high temperature drift.

11 See Figure 7 for details.

12 See Figure 9 for details.

13 VBIAS0 can be used for sourcing the offset voltage to external amplifiers.

14 High speed DAC offset calibration can remove this error. See the High Speed DAC Calibration Options section for details.

15 Measured using the box method.

16 The watchdog can be turned off during system initialization.

17 IOVDD can optionally be powered from a 1.8 V supply rail.

ADC RMS NOISE SPECIFICATIONS

The internal 1.82 V reference is used for all measurements.

Note that there is a correction factor of 1.835 V introduced to the ADC code to voltage conversion as a result of the ADC calibration. Although

a 1.82 V reference is used to calibrate the ADC offset and gain, 1.835/1.82 factor is needed to be multiplied during the calibration. If the ADC is

calibrated and there is a hardware reset, the calibration registers clear to the default value. The low power TIA gain resistor must be calibrated

regularly because this resistor has a high temperature drift.

ADC RMS Noise: Digital Filter Settings

Table 2 provides the rms noise specifications for the ADC with different ADC digital filter settings.

Table 2. ADC RMS Noise1

Update Rate

(Hz)

Sinc3 Oversampling Rate

(OSR)

Sinc2 OSR

Gain = 1 rms

Noise (μV)

Gain = 1.5 rms

Noise (μV)

Gain = 2 rms

Noise (μV)

Gain = 4 rms

Noise (μV)

Gain = 9 rms

Noise (μV)

200,000

Not applicable

72.43

49.732

37.83

18.93

8.62

9090

29.29

19.59

10.4

6.687

4.42

900

178

24.0

17.11

12.832

6.416

1.018

1 Noise can be reduced if ADC sample rate is reduced using the sinc2 filter.

ADC RMS Noise: Peak-to-Peak Effective Bits

Table 3 provides the rms and peak-to-peak effective bits based on the noise results in Table 2 for various PGA gain settings (peak-to-peak

effective bits results are shown in parentheses). To calculate the rms bits, use the following equation:

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