AD5941 datasheet(17/143 Pages) AD

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Data Sheet

AD5940/AD5941

SPECIFICATIONS

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Rev. D | 17 of 143

log2 ((2 × Input Range)/RMS Noise)

(1)

where:

Input Range is the input voltage range to the ADC.

RMS Noise is the rms of the noise.

To calculate the peak-to-peak effective bits, use the following equation:

log2 ((2 × Input Range)/(6.6 × RMS Noise))

(2)

Table 3. ADC Effective Bits Based on RMS Noise

Update Rate (Hz)

Sinc3

OSR

Sinc2 OSR

Gain = 1

Gain = 1.5

Gain = 2

Gain = 4

Gain = 9

Settling Time1 Settling Time2

200,000

Not applicable 14.6 (11.9 p‑p) 15 (12.4 p-p)

14.95 (12.23

p‑p)

14.95 (12.23

p‑p)

14.9 (12.15

p‑p)

16.25 μs

9090

15 (13.18 p‑p) 15 (13.8 p-p)

15 (14.09 p‑p)

15 (13.73 p‑p)

15 (13.15 p‑p)

236.25 μs

900

178

15 (13.47 p‑p) 15 (13.96 p‑p) 15 (13.8 p‑p)

15 (13.79 p‑p)

15 (15 p-p)

2.245 ms

37 ms

1 Settling time except for 50 Hz and 60 Hz notch filter enables.

2 Settling time including 50 Hz and 60 Hz notch filter enables.

SPI TIMING SPECIFICATIONS

MOSI and MISO are launched on the falling edge of SCLK and sampled on the rising edge of SCLK by the host and the AD5940/AD5941,

respectively. IOVDD = 2.8 V − 3.6 V and 1.8 V ±10%, unless otherwise noted.

Table 4.

Parameter

Time

Unit

Description

190

ns maximum

CS falling edge to MISO setup time

ns minimum

CS low to SCLK setup time

ns minimum

SCLK high time

ns minimum

SCLK low time

62.5

ns minimum

SCLK period

ns maximum

SCLK falling edge to MISO delay

ns minimum

MOSI to SCLK rising edge setup time

ns minimum

MOSI to SCLK rising edge hold time

ns minimum

SCLK falling edge to hold time CS

t10

ns minimum

CS high time

tWK

μs typical

AD5940/AD5941 wake-up time (not shown in Figure 3)

SPI Timing Diagram

Figure 3. SPI Interface Timing Diagram

AD5941 Datasheet(PDF) 17 Page - Analog Devices

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