AD5941 datasheet(13/143 Pages) AD

13 / 143 page

Data Sheet

AD5940/AD5941

SPECIFICATIONS

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Rev. D | 13 of 143

Table 1. (Continued)

Parameter

Symbol

Min

Typ

Max

Unit

Test Conditions/Comments

Full-Scale Error2, 14

Positive

600

630

650

Gain = 2, DAC code = 0xE00

15.1

Gain = 0.05, DAC code = 0xE00

Negative

−660

−640

−620

Gain = 2, DAC code = 0x200

−15.1

Gain = 0.05, DAC code = 0x200

Gain Error Drift over Temperature2

Gain = 2

11.5

µV/°C

Gain = 0.05

0.33

µV/°C

Offset Error (Midscale)

Measured at an output of the excitation loop across RCAL;

DAC code = 0x800

±25

Gain = 2

±0.5

Gain = 0.05

Offset Error Drift over Temperature

Gain = 2

µV/°C

Gain = 0.05

µV/°C

DC PSRR2

DC variation due to AVDD supply changes

PGA, Programmable Gain2

0.05

Gain

Reconstruction Filter

3 dB Corner Frequency Accuracy

±5

Programmable to 50 kHz, 100 kHz, and 250 kHz

Allowed External Load Capacitance2

SE0, DE0, AINx, and RCAL0/RCAL1 pins

<80 kHz (Low Power Mode)

100

>80 kHz (High Power Mode)

Overcurrent Limit Protection2

Amplifier attempts to limit the source/sink current to this

value via the internal clamp

Allowed Duration of Overcurrent Limit2

sec

Allowed Frequency of Overcurrent

Conditions2

Per hour

Short-Circuit Protection2

When amplifier output is shorted to ground

SWITCH MATRIX

Switches on analog front end before ADC mux

On Resistance2

RON

Characterized with a voltage sweep from 0 V to AVDD;

production tested at 2.8 V

Current Carrying Switches

Ω

Tx/TR1 switches, except T5 and T7

Ω

T5 and T7 switches only

Ω

Dx/DR0 switches

Noncurrent Carrying Switches

kΩ

Nx/Nxx and Px/Pxx switches

DC Off Leakage

370

Analog input pin used for test driven to 0.3 V

DC On Leakage2

530

2000

Analog input pin used for test driven to 0.3 V

TEMPERATURE SENSOR

Resolution

0.3

°C

Accuracy

±2

°C

Measurement taken immediately after exiting hibernate

mode; user single-point calibration required

POWER-ON RESET

POR

Refers to voltage on DVDD pin

POR Trip Level

Power-On

1.59

1.62

1.72

Power-Down2

1.799

1.8

1.801

POR Hysteresis1

Delay Between POR Power-On and

Power-Down Trip Levels2

110

After DVDD passes POR power-on trip level, DVDD must

remain at or above power-down level for this period

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