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AD5941 Datasheet(PDF) 7 Page - Analog Devices |
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AD5941 Datasheet(HTML) 7 Page - Analog Devices |
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7 / 143 page  Data Sheet AD5940/AD5941 SPECIFICATIONS analog.com Rev. D | 7 of 143 AVDD = DVDD = 2.8 V to 3.6 V; the maximum difference between supplies = 0.3 V; IOVDD = 1.8 V ± 10% and 2.8 V to 3.6 V; the ADC reference, excitation, DAC, and amplifier = 1.82 V, internal reference; low power DAC reference = 2.5 V, internal reference; TA = −40°C to +85°C for the AD5940 and AD5941, unless otherwise noted. TA = −40°C to 105°C for the AD5941W, unless otherwise noted. Table 1. Parameter Symbol Min Typ Max Unit Test Conditions/Comments BASIC ADC SPECIFICATIONS Pseudo differential mode measured relative to ADC bias voltage (voltage on VBIAS_CAP1 pin, 1.11 V), unless otherwise noted; specifications based on high speed mode, unless otherwise noted; ADC voltage channel calibrated in production with PGA gain = 1.5; AFE die clock for the analog domain (ACLK) = 32 MHz or 16 MHz, unless otherwise noted Data Rate2 fSAMPLE 400 kSPS High speed mode; decimation factor = 4 200 kSPS Normal mode; decimation factor = 4 Resolution2 16 Bits Number of data bits Integral Nonlinearity2 INL Normal Mode −4 ±2.0 +4 LSB PGA gain = 1.5, 1.82 V internal reference,1 LSB = 1.82 V ÷ 215 ÷ PGA gain −5.6 ±2.0 +4.7 LSB PGA gain = 9, 1.82 V internal reference Differential Nonlinearity2 DNL Normal Mode −0.99 ±0.9 +2.5 LSB PGA gain = 1.5, 1.82 V internal reference; 1 LSB = 1.82 V ÷ 215 ÷ PGA gain, no missing codes DC Code Distribution3 ±6 LSB PGA gain = 1.5, low power mode, ADC input = 0.9 V; ADC output data rate = 200 kSPS; 1 LSB = 1.82 V ÷ 215 ±6 LSB Input channel is low power TIA = 1 µA, RTIA = 512 kΩ, RLOAD = 10 Ω, ADC output data rate = 200 kSPS ±6 LSB Input channel is high speed TIA = 1 µA, RTIA = 10 kΩ, RLOAD = 100 Ω, ADC output data rate = 200 kSPS ADC ENDPOINT ERRORS Offset Error Low Power Mode −600 ±200 +600 µV PGA gain = 1.5, low power mode, all channels except AIN3 −620 ±200 +880 µV PGA gain = 1.5, AIN3 only High Power Mode2, 4 −1.1 ±0.5 +1.4 mV PGA gain = 1.5 Drift over Temperature2 ±3 µV/°C Using 1.82 V internal reference Offset Matching ±2 LSB Matching compared to AIN3 Full-Scale Error −1000 ±400 +800 µV PGA gain = 1.5, excluding internal channels and AIN3; both negative and positive full scale; error at both endpoints −1000 +1000 µV PGA gain = 1.5, AIN3 only High Power Mode2, 4 −2.2 ±0.9 +1.82 mV PGA gain = 1.5 Internal Channels2 0.2 0.75 % FS AVDD/2, DVDD/2, VBIAS_CAP, VREF_2V5, VREF_1V82, AVDD_REG Gain Drift over Temperature2 −3 ±1 +3 µV/°C Full-scale error drift minus offset error drift Gain Error Matching ±3 LSB Mismatch from channel to channel PGA Mismatch Error2 ADC offset and gain calibration5, 6, 7, 8 with a gain value of 1.5 PGA Gain = 1 to 1.5 −0.2 +0.1 +0.3 % PGA Gain = 1.5 to 2 −0.2 +0.1 +0.3 % PGA Gain = 2 to 4 −0.65 +0.2 +0.65 % PGA Gain = 4 to 9 −0.65 +0.2 +0.65 % ADC DYNAMIC PERFORMANCE fIN = 20 kHz sine wave, fSAMPLE = 200 kSPS; using AINx voltage input channels; PGA gain = 1.5 Signal-to-Noise Ratio SNR Includes distortion and noise components |
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