Data Sheet

AD1933

Rev. E | Page 23 of 28

ADDITIONAL MODES

The AD1933 offers several additional modes for board level

design enhancements. To reduce the EMI in board level design,

serial data can be transmitted without an explicit BCLK. See

Figure 19 for an example of a DAC TDM data transmission

mode that does not require high speed DBCLK. This configu-

ration is applicable when the AD1933 master clock is generated

by the PLL with the DLRCLK as the PLL reference frequency.

To relax the requirement for the setup time of the AD1933 in

cases of high speed TDM data transmission, the AD1933 can

latch in the data using the falling edge of DBCLK. This effectively

dedicates the entire BCLK period to the setup time. This mode

is useful in cases where the source has a large delay time in the

serial data driver. Figure 20 shows this pipeline mode of data trans-

mission. Both the BLCK-less and pipeline modes are available.

DLRCLK

INTERNAL

DBCLK

DSDATAx

DLRCLK

INTERNAL

DBCLK

TDM-DSDATAx

32 BITS

Figure 19. Serial DAC Data Transmission in TDM Format Without DBCLK (Applicable Only If PLL Locks to DLRCLK)

DLRCLK

DBCLK

DSDATAx

DATA MUST BE VALID

AT THIS BCLK EDGE

MSB

Figure 20. I2S Pipeline Mode in DAC Serial Data Transmission (Applicable in Stereo and TDM Useful for High Frequency TDM Transmission)