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EPR-9 Datasheet(PDF) 6 Page - Power Integrations, Inc. |
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EPR-9 Datasheet(HTML) 6 Page - Power Integrations, Inc. |
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6 / 32 page ![]() 5 W Universal Input Dual Output Isolated TNY266 03-April-2001 4 Circuit Description This circuit was designed for Home Appliance applications. The design for this had three main drivers: low cost, high ambient temperature operation and input voltage surge withstand. There are two input protection configurations, "1" (2 kV surge) on page 4 and "2" (6 kV) on page 5. Configuration "1" has a 33 Ω, 3 W fusible resistor (R1) which limits the 2 kV voltage surge current such that the peak charging voltage on C2 does not exceed the breakdown voltage of U1 (TNY266). R1 also functions as a fuse, opening any short that might occur on the primary side. (Pico II, series 263, Littelfuse or TR5, series 370, Wickmann) can be used (if R1 is unavailable in low wattage to ensure fusing). - Configuration "2" has two 47 Ω, energy rated resistors (R7, R8), which, along with the varistor RV1, form a voltage divider. The life of RV1 is endless if its energy rating is not exceeded (see Fig. 8.7.1). The energy rated resistors R7, R8 are not fusible and the short circuit current being limited (~0.9 A at 85 VAC) by R7, R8 (94 Ω), and a 0.5 A fast acting fuse The efficiency of the 6 kV configuration can be improved at the expense of the total number of 6 kV surges protection, by reducing the value of R7, R8 up to zero. Downstream of the input protection circuits, the operation of the two configurations is identical. In this Home Appliance application (refer to page 4 or 5 of this report), the AC input is rectified and filtered by D1-D4, C1 and C2 to create a high voltage DC buss which is connected to T1. Inductor L1 forms a pi- filter in conjunction with C1 and C2. The resistor R2 damps resonance in inductor L1. The frequency jitter in U1 allows the unit to meet worldwide conducted EMI standards using a simple pi-filter in combination with a small value Y1-capacitor C4 and a proper PCB layout. The built-in circuitry of U1 practically eliminates the audio noise permitting the use of ordinary varnished transformers. VR1 and D5 form a clamp circuit that limits the turn-off voltage spike to a safe level on the U1-DRAIN pin. The secondary windings are stacked to improve the cross regulation. The 5 V winding is rectified and filtered by D6, C5 with additional filtering provided by L2, C7 to give the 5 VDC output. The 5 VDC output voltage is determined by the sum of the voltage drops across the optocoupler U2 and the Zener diode VR2. Resistor R3 (AC gain of the circuit) limits the current through U2, improving its response time. Resistor R4 sets the bias current for VR2. The 12 V winding is rectified and filtered by D7, C6 to provide the 12 VDC output. A minimum loading is necessary on the two outputs to keep them within the specified limits. The primary-to-secondary isolation is provided by using parts/materials (opto/transformer insulation) with the correct level of isolation and creepage distances (opto slot/transformer bobbin). Also the C4 value (while allowing common mode noise current path) has to keep the leakage current below the standard (IEC950) accepted value. The 5 VDC and 12 VDC monitoring light emitting diodes (LED2, LED1) and R6, R5 are optional, and have been included in this circuit for troubleshooting convenience. The board has a small, secondary side prototyping area for alternate voltage regulation control. Test points TP1 (U1-SOURCE) and TP2 (U1-DRAIN) are provided for ease of monitoring VDS. TP2 jumper can be replaced with a longer one to allow a current probe insertion for Id monitoring. Page 6 of 32 Power Integrations, Inc. Tel: +1 408 414 9200 Fax: +1 408 414 9201 www.powerint.com |
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