18F2420 datasheet(3/16 Pages) MICROCHIP

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DS80209D-page 3

PIC18F2420/2520/4420/4520

Module: ECCP

When the ECCP1 auto-shutdown feature is con-

figured for automatic restart by setting the PRSEN

bit (PWM1CON<7>), the pulse terminates immedi-

ately in a shutdown event. In addition, the pulse

may restart within the period if the shutdown

condition expires. This may result in the generation

of short pulses on the PWM output(s).

Work around

Configure the auto-shutdown for software restart

by clearing the PRSEN bit (PWM1CON<7>). The

PWM

can

re-enabled

clearing

the

ECCPASE bit (ECCP1AS<7>) after the shutdown

condition expires.

Date Codes that pertain to this issue:

All engineering and production devices.

Module: ECCP

When monitoring a shutdown condition using a bit

test on the ECCPASE bit (ECCP1AS<7>), or

performing a bit operation on the ECCPASE bit,

the device may produce unexpected results.

Work around

Before performing a bit test or bit operation on the

ECCPASE bit, copy the ECCP1AS register to the

working register and perform the operation there.

By avoiding these operations on the ECCPASE bit

in the ECCP1AS register, the module will operate

normally.

In Example 1, ECCPASE bit operations are

performed on the W register.

EXAMPLE 1:

Date Codes that pertain to this issue:

All engineering and production devices.

Module: ECCP

The auto-shutdown source, FLT0, has inverse

polarity from the description in Section 16.4.7

“Enhanced PWM Auto-Shutdown” of the Device

Data Sheet. A logic high-voltage level on FLT0 will

generate a shutdown on ECCP1.

Work around

None.

Date Codes that pertain to this issue:

All engineering and production devices.

Module: ECCP and CCP

The CCP1 and CCP2 configured for PWM mode,

with 1:1 Timer2 prescaler and duty cycle set to the

period minus 1, may result in the PWM output(s)

remaining at a logic low level.

Clearing the PR2 register to select the fastest

period may also result in the output(s) remaining at

a logic low output level.

Work around

To ensure a reliable waveform, verify that the

selected duty cycle does not equal the 10-bit

period minus 1 prior to writing these locations, or

use 1:4 or 1:16 Timer2 prescale. Also, verify the

PR2 register is not written to 00h.

All other duty cycle and period settings will function

as described in the Device Data Sheet.

The ECCP and CCP modules remain capable of

10-bit accuracy.

Date Codes that pertain to this issue:

All engineering and production devices.

10. Module: ECCP

ECCP1

configured

for

auto-shutdown

with

Comparator 1 corrupts the PWM duty cycle pulse.

In addition, it does not always synchronize the

pulse to the beginning of the period and the end of

the pulse can occur at any time within the period.

Work around

Use FLT0 for the auto-shutdown source. Applica-

tions which can tolerate a shutdown response time

of several TCYs may use the comparator interrupt

flag to detect a shutdown event and disable the

PWM

clearing

the

EECPASE

bit

(ECCP1AS<7>).

Date Codes that pertain to this issue:

All engineering and production devices.

11. Module: ECCP

When the shutdown state of the PWM pin(s) is

configured to tri-state the outputs, the device may

consume higher than expected current during the

shutdown event.

Work around

Configure the PWM output for either a high or low

logic

state

during

the

shutdown

via

the

PSSAC1:PSSAC0 (ECCP1AS<3:2>) and PSSBD1:

PSSBD0 (ECCP1AS<1:0>) bits. Clearing the auto-

shutdown event will return the device to normal

current consumption levels.

Date Codes that pertain to this issue:

All engineering and production devices.

MOVF

ECCP1AS, W

BTFSC

WREG, ECCPASE

BRA

SHUTDOWN_ROUTINE

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