18F2420 datasheet(7/16 Pages) MICROCHIP

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DS80209D-page 7

PIC18F2420/2520/4420/4520

23. Module: Interrupts

If an interrupt occurs during a two-cycle instruction

that modifies the STATUS, BSR or WREG register,

the unmodified value of the register will be saved

to the corresponding Fast Return (Shadow)

the unmodified value will be restored to the

STATUS, BSR or WREG register.

For example, if a high priority interrupt occurs

during the instruction, MOVFF TEMP, WREG, the

MOVFF

instruction will be completed and WREG

will be loaded with the value of TEMP before

branching to ISR. However, the previous value of

WREG will be saved to the Fast Return register

during ISR branching. Upon return from the

interrupt with a fast return, the previous value of

WREG in the Fast Return register will be written to

WREG. This results in WREG containing the value

it had before execution of MOVFF TEMP, WREG.

Affected instructions are:

MOVFF

Fs, Fd

where Fd is WREG, BSR or STATUS;

MOVSF

Zs, Fd

where Fd is WREG, BSR or STATUS; and

MOVSS

[Zs], [Zd]

where the destination is WREG, BSR or STATUS.

Work around

1. Assembly Language Programming:

a) If any two-cycle instruction is used to modify

the WREG, BSR or STATUS register, do not

use the RETFIE FAST instruction to return

from the interrupt. Instead, save/restore

WREG, BSR and STATUS via software per

Example 9-1 in the Device Data Sheet. Alter-

natively, in the case of MOVFF, use the MOVF

instruction to write to WREG instead. For

example, use:

MOVF

TEMP, W

MOVWF

BSR

instead of: MOVFF TEMP, BSR.

b) As another alternative, the following work

around shown in Example 2 can be used.

This example overwrites the Fast Return

the fast option in the high priority service

routine.

EXAMPLE 2:

ISR @ 0x0008

CALL

Foo, FAST

; store current value of WREG, BSR, STATUS for a second time

Foo:

POP

; clears return address of Foo call

; insert high priority ISR code here

RETFIE

FAST

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