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AD9163BBCZ Datasheet(PDF) 92 Page - Analog Devices |
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AD9163BBCZ Datasheet(HTML) 92 Page - Analog Devices |
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92 / 126 page  AD9163 Data Sheet Rev. D | Page 92 of 126 Hex. Addr. Name Bits Bit Name Settings Description Reset Access 0 LINK_EN This bit brings up the JESD204B receiver when all link parameters are programmed and all clocks are ready. 0x0 R/W 0x302 DYN_LINK_LATENCY_0 [7:5] RESERVED Reserved. 0x0 R [4:0] DYN_LINK_LATENCY_0 Measurement of the JESD204B link delay (in PCLK units). Link 0 dynamic link latency. Latency between current deframer LMFC and the global LMFC. 0x0 R 0x304 LMFC_DELAY_0 [7:5] RESERVED Reserved. 0x0 R [4:0] LMFC_DELAY_0 Fixed part of the JESD204B link delay (in PCLK units). Delay in frame clock cycles for global LMFC for Link 0. 0x0 R/W 0x306 LMFC_VAR_0 [7:5] RESERVED Reserved. 0x0 R [4:0] LMFC_VAR_0 Variable part of the JESD204B link delay (in PCLK units). Location in Rx LMFC where JESD204B words are read out from buffer. This setting must not be more than 10 PCLKs. 0x1F R/W 0x308 XBAR_LN_0_1 [7:6] RESERVED Reserved. 0x0 R [5:3] SRC_LANE1 Select data from SERDIN0±, SERDIN1±, …, or SERDIN7± for Logic Lane 1. 0x1 R/W 000 Data is from SERDIN0±. 001 Data is from SERDIN1±. 010 Data is from SERDIN2±. 011 Data is from SERDIN3±. 100 Data is from SERDIN4±. 101 Data is from SERDIN5±. 110 Data is from SERDIN6±. 111 Data is from SERDIN7±. [2:0] SRC_LANE0 Select data from SERDIN0±, SERDIN1±, …, or SERDIN7± for Logic Lane 0. 0x0 R/W 000 Data is from SERDIN0±. 001 Data is from SERDIN1±. 010 Data is from SERDIN2±. 011 Data is from SERDIN3±. 100 Data is from SERDIN4±. 101 Data is from SERDIN5±. 110 Data is from SERDIN6±. 111 Data is from SERDIN7±. 0x309 XBAR_LN_2_3 [7:6] RESERVED Reserved. 0x0 R [5:3] SRC_LANE3 Select data from SERDIN0±, SERDIN1±, …, or SERDIN7± for Logic Lane 3. 0x3 R/W 000 Data is from SERDIN0±. 001 Data is from SERDIN1±. 010 Data is from SERDIN2±. 011 Data is from SERDIN3±. 100 Data is from SERDIN4±. 101 Data is from SERDIN5±. 110 Data is from SERDIN6±. 111 Data is from SERDIN7±. |
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