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TDA8003TS/C2 Datasheet(PDF) 6 Page - NXP Semiconductors

Part # TDA8003TS/C2
Description  I2C-bus SIM card interface
PDF  24 Pages
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Manufacturer  PHILIPS [NXP Semiconductors]
Direct Link  http://www.nxp.com
Logo PHILIPS - NXP Semiconductors

TDA8003TS/C2 Datasheet(HTML) 6 Page - NXP Semiconductors

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2000 Apr 20
6
Philips Semiconductors
Product specification
I2C-bus SIM card interface
TDA8003TS
Fig.2 Pin configuration.
handbook, halfpage
PWROFF
S1
PGND
S3
VDDP
S4
S2
VUP
I/O
SGND
CLK
VCC
SIMCLK
SAD1
SAD0
SIMERR
SDA
VDDI
SCL
SIMI/O
PRES
DEL
VDDS
RST
1
2
3
4
5
6
7
8
9
10
11
12
24
23
22
21
20
19
18
17
16
15
14
13
TDA8003TS
MGR435
FUNCTIONAL DESCRIPTION
Figure 1 shows the block diagram of the TDA8003TS.
The functional blocks are described in the following
sections. It is assumed that the reader of this specification
is aware of GSM11.11 and ISO 7816 terminology.
I2C-bus control
The I2C-bus interface is used:
• To configure the clock to the card in active mode
(1
2fSIMCLK and 14fSIMCLK)
• To configure the clock to the card in power reduction
mode (stop LOW, stop HIGH or
±1.25 MHz derived
from the internal oscillator)
• To select operation with a 3 or 5 V card
• To start or stop sessions (cold reset)
• To initiate a warm reset
• To enter or leave the Power-down mode
• To request the status (card present or not, hardware
problem occurred, unresponsive card after activation,
supply drop-out detected by the voltage supervisor, card
powered or not)
• To configure SIMI/O and I/O in high-impedance (for use
of several TDA8003TS in parallel).
The structure of the I2C-bus data frames is as follows:
• Commands to the TDA8003TS:
– START/ADDRESS/WRITE
– COMMAND BYTE
– STOP.
The fixed address is 01001XY. X and Y are defined by
the logic levels on pins SAD1 and SAD0 as shown in
Table 1 (connect to ground for logic 0; connect to VDDI
for logic 1). The command bits are described in Table 2.
The commands are executed on the rising edge of the
9th SCL pulse.
• Status from the TDA8003TS (see Table 4). The fixed
address is 01001XY. X and Y are defined by the logic
levels on pins SAD1 and SAD0 as shown in Table 1.
Table 1
Address selections
ADDRESS
SAD1
SAD0
48H
0
0
4AH
0
1
4CH
1
0
4EH
1
1



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