82546EB datasheet(14/47 Pages) INTEL

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82546EB — Networking Silicon

Datasheet

3.0

Signal Descriptions

Note:

The targeted signal names are subject to change without notice. Verify with your local Intel sales

office that you have the latest information before finalizing a design.

3.1

Signal Type Definitions

The signals of the 82546EB controller are electrically defined as follows:

3.2

PCI Bus Interface

When the Reset signal (RST#) is asserted, the 82546EB will not drive any PCI output or bi-

directional pins except the Power Management Event signal (PME#).

3.2.1

PCI Address, Data and Control Signals

Name

Definition

Input. Standard input only digital signal.

Output. Standard output only digital signal.

Tri-state. Bi-directional three-state digital input/output signal.

STS

Sustained Tri-state. Sustained digital three-state signal driven by one agent at a time.

An agent driving the STS pin low must actively drive it high for at least one clock before letting it

float. The next agent of the signal cannot drive the pin earlier than one clock after it has been

released by the previous agent.

Open Drain. Wired-OR with other agents.

The signaling agent asserts the OD signal, but the signal is returned to the inactive state by a

weak pull-up resistor. The pull-up resistor may require two or three clock periods to fully restore

the signal to the de-asserted state.

Analog. PHY analog data signal.

Power. Power connection, voltage reference, or other reference connection.

Reserved.

Symbol

Type

Name and Function

AD[63:0]

Address and Data. Address and data signals are multiplexed on the same PCI pins. A

bus transaction includes an address phase followed by one or more data phases.

The address phase is the clock cycle when the Frame signal (FRAME#) is asserted

low. During the address phase AD[63:0] contain a physical address (64 bits). For I/O,

this is a byte address, and for configuration and memory, a DWORD address. The

82546EB device uses little endian byte ordering.

During data phases, AD[7:0] contain the least significant byte (LSB) and AD[63:56]

contain the most significant byte (MSB).

The 82546EBcontroller may optionally be connected to a 32-bit PCI bus. On the 32-bit

bus, AD[63:32] and other signals corresponding to the high order byte lanes do not

participate in the bus cycle.

82546EB Datasheet(PDF) 14 Page - Intel Corporation

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