Datasheet

23

4.6

Timing Specifications

4.6.1

PCI/PCI-X Bus Interface

4.6.1.1

PCI/PCI-X Bus Interface Clock

4.6.1.2

PCI/PCI-X Bus Interface Timing

Table 12. PCI/PCI-X Bus Interface Clock Parameters

Symbol

a. Rise and fall times are specified in terms of the edge rate measured in V/ns. This slew rate must be met across the minimum

peak-to-peak portion of the clock waveform as shown.

PCI-X 133

MHz

PCI-X 66 MHz

PCI 66MHz

PCI 33 MHz

Units

Min

Max

Min

Max

Min

Max

Min

Max

TCYC

CLK cycle time

7.5

201520153030

ns

TH

CLK high time

3

6

6

11

ns

TL

CLK low time

3

6

6

11

ns

CLK slew rate

1.541.541.5

4

1

4

V/ns

b. The minimum RST# slew rate applies only to the rising (de-assertion) edge of the reset signal and ensures that system noise

cannot render a monotonic signal to appear bouncing in the switching range.

50

50

50

50

mV/ns

Figure 3. PCI/PCI-X Clock Timing

Table 13. PCI/PCI-X Bus Interface Timing Parameters

Symbol

Parameter

PCI-X 133

MHz

PCI-X 66 MHz

PCI 66MHz

PCI 33 MHz

Units

Min

Max

Min

Max

Min

Max

Min

Max

TVAL

CLK to signal valid delay:

bussed signals

0.73.8

0.73.8

2

6

2

11

ns

TVAL

(ptp)

CLK to signal valid delay:

point-to-point signals

0.73.8

0.73.8

2

6

2

12

ns

TON

Float to active delay

0022

ns

TOFF

Active to float delay

7

7

14

28

ns

0.6 Vcc

0.2 Vcc

0.5 Vcc

0.4 Vcc

0.3 Vcc

Tcyc

Th

Tl

0.4 Vcc p-to-p

(minimum)

3.3 V Clock