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SPSB100 Datasheet(PDF) 173 Page - STMicroelectronics |
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SPSB100 Datasheet(HTML) 173 Page - STMicroelectronics |
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173 / 214 page  Digital FSM states Spec states/modes Binary USER_NVM_PROG_2_COMPLETE U-NVM-PROG-2 100001 USER_NVM_PROG_3 100010 USER_NVM_PROG_3_COMPLETE 100011 USER_NVM_PROG_4 100100 USER_NVM_PROG_4_COMPLETE 100101 Table 238. DSR5 (0x25) LSB Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 0 (RC1L) 0 (RC1L) 0 (RC1L) 0 (RC1L) 0 (RC1L) 0 (RC1L) 0 (RC1L) 0 (RC1L) FORCED_SLEEP_POWUP FSM_TO_REC2 REC2_FROM_DO_POWER_CYCLE_1 REC2_FROM_DO_POWER_CYCLE_0 CRC3 CRC2 CRC1 CRC0 Forced sleep power up bit Finite state machine to REC2 bit REC2 from power cycle bit 1 REC2 from power cycle bit 0 Cyclic redundancy checking bit 3 Cyclic redundancy checking bit 2 Cyclic redundancy checking bit 1 Cyclic redundancy checking bit 0 Table 239. DSR5 (0x25) LSB description Bit Name Description 7 FORCED_SLEEP_POWUP 1: state machine reaches DEEP-SLEEP after 3 attend to power-up 6 FSM_TO_REC2 Functional state machine state before reaching REC2 1: REC1 Bit is latched until a “read and clear” command 0: ACTIVE 5 REC2_FROM_DO_POWER_CYCLE_1 00: Default 01: REC2 entered after a DO_POWER_CYCLE command in ACTIVE state 1x: REC2 entered after a DO_POWER_CYCLE command in REC-1 state 4 REC2_FROM_DO_POWER_CYCLE_0 3 CRC 3 2 CRC 2 1 CRC 1 0 CRC 0 Table 240. DSR6 (0x26) MSB Bit 23 Bit 22 Bit 21 Bit 20 Bit 19 Bit 18 Bit 17 Bit 16 - (R0) 0 (RC1L) 0 (RC1L) 0 (R) 0 (RC1L) 0 (RC1L) 0 (RC1L) 0 (RC1L) RES LP_READY SWDBG_VIO SWDBG_STATE RES RES RES RES Reserved Low power Ready bit Software debug VIO bit Software debug status Reserved bit Reserved bit Reserved bit Reserved bit Table 241. DSR6 (0x26) MSB description Bit Name Description 23 RES Reserved 22 LP_READY 1: Transition from full power to low power occurred. IRQ generated and this bit set when this occurs if not masked by MASK_LP_READY_IRQ 21 SWDBG_VIO SWDBG is linked to VIO up to the end of the timeout following the power-up sequence. If not masked, IRQ is generated and the watchdog starts with L.O.W. 20 SWDBG_STATE state of SWDBG input pin with VIO thresholds SPSB100 SPI registers DS14640 - Rev 1 page 173/214 |
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