PX3SE datasheet(53/54 Pages) ROCKCHIP

53 / 54 page

PX3 SE Datasheet

Rev 1.2

CAP, the LINEL and LINER have the same function as the MICL and MICR. The R1 and C3

are formed a filter for the MIC, and the R2, C4 have same function. The VREF_MIC is used

for bias the MIC through a resistor. The resistor value should be changed according the

MIC. The AVDD should be supplied by 3.3V. The CAP connected with AVDD should be

placed as close as possible

The VCM is connected with GND through a 4.7Uf CAP. The CAP should be placed as close as

possible. The VOUTL and VOUTR could be connected with a speaker or an earphone. When

connecting with a speaker, they could connect it directly. When connecting with an

earphone, they should connect it through a 100uF CAP. The J19 and J20 are dip-switches,

and you could select a speaker or an earphone as the output.

4.6 PX3 SE Power on reset descriptions

NPOR is hardware reset signal from out-chip, which is filtered glitch to obtain signal

sysrstn. To make PLLs work normally, the PLL reset signal (pllrstn) must maintain high for

more than 1us, and PLLs start to lock when pllrstndeassert, andthe PLL max lock time is

1500 PLL REFCLK cycles. And then the system will wait about 138us, and then deactive

reset signal chiprstn. The signal chiprstn is used to generate output clocks in CRU. After

CRU start output clocks, the system waits again for 512cycles (21.3us) to deactive signal

rstn_pre, which is used to generate power on reset of all IP.

npor

sysrstn

pllrstn

1.3us

chiprstn

138us

rstn_pre

(IP reset)

21.3us

Fig.4-9 PX3 SE reset signals sequence

PX3SE Datasheet(PDF) 53 Page - Rockchip Electronics Co., Ltd