PX3SE datasheet(10/54 Pages) ROCKCHIP

10 / 54 page

PX3 SE Datasheet

Rev 1.2

different application scenes



Timer



6 on-chip 64bits Timers in SoC with interrupt-based operation



Provide two operation modes: free-running and user-defined count



Support timer work state checkable



Fixed 24MHz clock input



PWM



Four on-chip PWMs with interrupt-based operation



Programmable pre-scaled operation to bus clock and then further scaled



Embedded 32-bit timer/counter facility



Support capture mode



Support continuous mode or one-shot mode



Provides reference mode and output various duty-cycle waveform



WatchDog



32 bits watchdog counter width



Counter clock is from apb bus clock



Counter counts down from a preset value to 0 to indicate the occurrence of a

timeout



WDT can perform two types of operations when timeout occurs:



Generate a system reset



First generate an interrupt and if this is not cleared by the service routine by

the time a second timeout occurs then generate a system reset



Programmable reset pulse length



Totally 16 defined-ranges of main timeout period



Bus Architecture



128bit/64-bit/32-bit multi-layer AXI/AHB/APB composite bus architecture



5 embedded AXI interconnect



CPU interconnect with four 64-bits AXI masters, one 64-bits AXI slaves, one

32-bits AHB master and lots of 32-bits AHB/APB slaves



PERI interconnect with two 64-bits AXI masters, one 64-bits AXI slave, five 32-

bits AHB masters and lots of 32-bits AHB/APB slaves



Display interconnect with three 128-bits AXI master, four 64-bits AXI masters

and one 32-bits AHB slave



GPU interconnect with one 128-bits AXI master with point-to-point AXI-lite

architecture and 32-bits APB slave



VCODEC interconnect also with two 64-bits AXI master and two 32-bits AHB

slave, they are point-to-point AXI-lite architecture



Flexible different QoS solution to improve the utility of bus bandwidth



Interrupt Controller



Support 3 PPI interrupt source and 74 SPI interrupt sources input from different

components inside PX3 SE



Support 16 softwre-triggered interrupts



Input interrupt level is fixed , only high-level sensitive



Two interrupt outputs (nFIQ and nIRQ)separatelyfor each Cortex-A7, both are low-

level sensitive



Support different interrupt priority for each interrupt source, and they are always

software-programmable



DMAC



Micro-code programming based DMA



The specific instruction set provides flexibility for programming DMA transfers



Linked list DMA function is supported to complete scatter-gather transfer

PX3SE Datasheet(PDF) 10 Page - Rockchip Electronics Co., Ltd

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