 |
Electronic Components Datasheet Search |
|
|
Electronic Components Datasheet Search |
|
AD7768 Datasheet(PDF) 17 Page - Analog Devices |
|
|
|||||||||||||||||||||||||||||
AD7768 Datasheet(HTML) 17 Page - Analog Devices |
|
|
17 / 106 page  Data Sheet AD7768/AD7768-4 SPECIFICATIONS analog.com Rev. C | 17 of 106 Table 4. SPI Control Interface Timing1 Parameter Description Test Conditions/Comments Min Typ Max Unit t17 SCLK period 100 ns t18 CS falling edge to SCLK rising edge 26.5 ns t19 SCLK falling edge to CS rising edge 27 ns t20 CS falling edge to data output enable 22.5 40.5 ns t21 SCLK high time 20 50 ns t22 SCLK low time 20 50 ns t23 SCLK falling edge to SDO valid 15 ns t24 SDO hold time after SCLK falling 7 ns t25 SDI setup time 0 ns t26 SDI hold time 6 ns t27 SCLK enable time 0 ns t28 SCLK disable time 0 ns t29 CS high time 10 ns t30 CS low time fMOD = MCLK/4 1.1 × tMCLK ns fMOD = MCLK/8 2.2 × tMCLK ns fMOD = MCLK/32 8.8 × tMCLK ns 1.8 V IOVDD TIMING SPECIFICATIONS AVDD1A = AVDD1B = 5 V, AVDD2A = AVDD2B = 5 V, IOVDD = 1.72 V to 1.88 V (DREGCAP tied to IOVDD), Input Logic 0 = DGND, Input Logic 1 = IOVDD, CLOAD = 10 pF on DCLK pin, CLOAD = 20 pF on other digital outputs, TA = −40°C to +105°C. Table 5. Data Interface Timing1 Parameter Description Test Conditions/Comments Min Typ Max Unit MCLK Master clock 1.15 34 MHz fMOD Modulator frequency Fast mode MCLK/4 Hz Median mode MCLK/8 Hz Low power mode MCLK/32 Hz t1 DRDY high time tDCLK − 10% 28 ns t2 DCLK rising edge to DRDY rising edge 2 ns t3 DCLK rising to DRDY falling −4.5 0 ns t4 DCLK rise to DOUTx valid 2.0 ns t5 DCLK rise to DOUTx invalid −4 ns t6 DOUTx valid to DCLK falling 8.5 tDCLK/2 ns t7 DCLK falling edge to DOUTx invalid 8.5 tDCLK/2 ns t8 DCLK high time, DCLK = MCLK/1 50:50 CMOS clock tDCLK/2 tDCLK/2 (tDCLK/2) + 5 ns t8a = DCLK = MCLK/2 tMCLK ns t8b = DCLK = MCLK/4 2 × tMCLK ns t8c = DCLK = MCLK/8 4 × tMCLK ns t9 DCLK low time DCLK = MCLK/1 50:50 CMOS clock (tDCLK/2) − 5 tMCLK/2 tDCLK/2 ns t9a = DCLK = MCLK/2 tMCLK ns t9b = DCLK = MCLK/4 2 × tMCLK ns t9c = DCLK = MCLK/8 4 × tMCLK ns t10 MCLK rising to DCLK rising CMOS clock 37 ns |
|
Link URL |
| Does ALLDATASHEET help your business so far? [ DONATE ] |
About Alldatasheet | Advertisement | Contact us | Privacy Policy | Link to Datasheet | Link Exchange | Manufacturer List All Rights Reserved©Alldatasheet.com |
| Russian : Alldatasheetru.com | Korean : Alldatasheet.co.kr | Spanish : Alldatasheet.es | French : Alldatasheet.fr | Italian : Alldatasheetit.com Portuguese : Alldatasheetpt.com | Polish : Alldatasheet.pl | Vietnamese : Alldatasheet.vn Indian : Alldatasheet.in | Mexican : Alldatasheet.com.mx | British : Alldatasheet.co.uk | New Zealand : Alldatasheet.co.nz |
|
Family Site : ic2ic.com |
icmetro.com |
English ▼
English
Chinese
German
Japanese
Russian
Korean
Spanish
French
Italian
Portuguese
Polish
Vietnamese
Indian
Mexican
British
New Zealand
