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Data Sheet

AD7768/AD7768-4

PIN CONFIGURATIONS AND FUNCTION DESCRIPTIONS

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Rev. C | 29 of 106

Table 10. AD7768-4 Pin Function Descriptions

Pin No.

Mnemonic

Type1

Description

FORMAT0

Format Selection. Hardwire the FORMAT0 pin to the required value in pin and SPI control mode. This pin sets

the number of DOUTx pins used to output ADC conversion data. The FORMAT0 pin is checked by the AD7768-4

on power-up, the AD7768-4 then remains in this data output configuration. See Table 34.

PIN/SPI

Pin Control/SPI Control. This pin sets the AD7768-4 control method.

Logic 0 = pin control mode for the AD7768-4. Pin control mode allows pin strapped configuration of the AD7768-4

by tying logic input pins to required logic levels. Tie logic pins (MODE0 to MODE4, DEC0 and DEC1, and

FILTER) as required for the configuration. See the Pin Control section for more details.

Logic 1 = SPI control mode for the AD7768-4. Use the SPI control interface signals (CS, SCLK, SDI, and SDO)

for reading and writing to the AD7768-4 memory map.

CLK_SEL

Clock Select.

Logic 0 = pull this pin low for the CMOS clock option. The clock is applied to Pin 32 (Connect Pin 31 to DGND).

Logic 1 = pull this pin high for the crystal or LVDS clock option. The crystal or LVDS clock is applied to Pin 31

and Pin 32. The LVDS option is available only in SPI control mode. A write is required to enable the LVDS clock

option.

VCM

Common-Mode Voltage Output. This pin outputs (AVDD1 − AVSS)/2 V, which is 2.5 V by default in pin control

mode. Configure this pin to (AVDD1 − AVSS)/2 V, 2.5 V, 2.14 V, or 1.65 V in SP control mode. When driving

capacitive loads larger than 0.1 µF, it is recommended to place a 50 Ω series resistor between the pin and the

capacitive load for stability. The VCM voltage output is associated with the Channel 0 circuitry. If Channel 0 is

put into standby mode, the VCM voltage output is also disabled for maximum power savings. Channel 0 must be

enabled while VCM is being used externally to the AD7768-4.

AVDD2A

Analog Supply Voltage. This pin is 2 V to 5.5 V with respect to AVSS.

REGCAPA

Analog LDO Regulator Output. Decouple this pin to AVSS with a 1 µF capacitor.

AVSS2A

Negative Analog Supply. This pin is nominally 0 V.

AIN0−

Negative Analog Input to ADC Channel 0.

AIN0+

Positive Analog Input to ADC Channel 0.

1 AI is analog input, P is power, DI/O is digital input/output, DI is digital input, DO is digital output, and AO is analog output.

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