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Data Sheet

AD7768/AD7768-4

PIN CONFIGURATIONS AND FUNCTION DESCRIPTIONS

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Rev. C | 23 of 106

Table 9. Pin Function Descriptions

Pin No.

Mnemonic

Type1

Description

In SPI control mode, the GPIOx pins, in addition to the FILTER/GPIO4 pin, form five general-purpose input/output pins

(GPIO4 to GPIO0).

ST0/CS

Standby 0/Chip Select Input.

In pin control mode, a Logic 1 places Channel 0 to Channel 3 into standby mode.

In SPI control mode, this pin is the active low chip select input to the SPI control interface. The VCM voltage output is

associated with the Channel 0 circuitry. If Channel 0 is put into standby mode, the VCM voltage output is also disabled

for maximum power savings. Channel 0 must be enabled while VCM is being used externally to the AD7768.

ST1/SCLK

Standby 1/Serial Clock Input.

In pin control mode, a Logic 1 on this pin places Channel 4 to Channel 7 into standby mode.

The crystal excitation circuitry is associated with the Channel 4 circuitry. If Channel 4 is placed into standby mode, the

crystal circuitry is also disabled for maximum power savings. Channel 4 must be enabled while the external crystal is

used on the AD7768.

In SPI control mode, this pin is the serial clock input pin for the SPI control interface.

DEC1/SDI

Decimation Rate Control Input 1/Serial Data Input.

In pin control mode, the DEC0 pin and DEC1 pin configure the decimation rate for all ADC channels. See Table 17 in the

Setting the Decimation Rate section for more information.

In SPI control mode, this pin is the serial data input pin used to write data to the AD7768 register bank.

DEC0/SDO

DI/O

Decimation Rate Control Input 0/Serial Data Output.

In pin control mode, the DEC0 pin and DEC1 pin configure the decimation rate for all ADC channels. See Table 17 in the

Setting the Decimation Rate section for more information.

In SPI control mode, this pin is the serial data output pin, allowing readback from the AD7768 registers.

DOUT7

DI/O

Conversion Data Output 7. This pin is synchronous to DCLK and framed by DRDY. This pin acts as a digital input

from a separate AD7768 device if configured in a synchronized multidevice daisy chain when the FORMATx pins are

configured as 01. To use the AD7768 in a daisy chain, hardwire the FORMATx pins as 01, 10, or 11, depending on

the best interfacing format for the application. When FORMATx is set to 01, 10, or 11, and daisy-chaining is not used,

connect this pin to ground through a pull-down resistor.

DOUT6

DI/O

Conversion Data Output 6. This pin is synchronous to DCLK and framed by DRDY. This pin acts as a digital input

from a separate AD7768 device if configured in a synchronized multidevice daisy chain. To use this pin in a daisy

chain, hardwire the FORMATx pins as 01, 10, or 11, depending on the best interfacing format for the application. When

FORMATx is set to 01, 10, or 11, and daisy chaining is not used, connect this pin to ground through a pull-down resistor.

DOUT5

Conversion Data Output 5. This pin is synchronous to DCLK and framed by DRDY.

DOUT4

Conversion Data Output 4. This pin is synchronous to DCLK and framed by DRDY.

DOUT3

Conversion Data Output 3. This pin is synchronous to DCLK and framed by DRDY.

DOUT2

Conversion Data Output 2. This pin is synchronous to DCLK and framed by DRDY.

DOUT1

Conversion Data Output 1. This pin is synchronous to DCLK and framed by DRDY.

DOUT0

Conversion Data Output 0. This pin is synchronous to DCLK and framed by DRDY.

DCLK

ADC Conversion Data Clock. This pin clocks conversion data out to the digital host (digital signal processor (DSP)/

field-programmable gate array (FPGA)). This pin is synchronous with DRDY and any conversion data output on DOUT0

to DOUT7, and is derived from the MCLK signal. This pin is unrelated to the control SPI interface.

DRDY

Data Ready. DRDY is a periodic signal output framing the conversion results from the eight ADCs. This pin is

synchronous to DCLK and DOUT0 to DOUT7.

RESET

Hardware Asynchronous Reset Input. After the device is fully powered up, it is recommended to perform a hard reset

using this pin or, alternatively, to perform a soft reset by issuing a reset over the SPI control interface.

XTAL1

Input 1 for Crystal or Connection to an LVDS Clock. When CLK_SEL is 0, connect XTAL1 to DGND. In SPI control

mode, when using a crystal source, the FILTER pin must be set to Logic 1 for correct operation. The crystal excitation

circuitry is associated with the Channel 4 circuitry. If Channel 4 is put into standby mode, the crystal circuitry is also

disabled for maximum power savings. Channel 4 must be enabled while the external crystal is used on the AD7768.

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