AD9915SLASHPCBZ datasheet(33/51 Pages) AD

33 / 51 page

Data Sheet

AD9915

PROGRAMMING AND FUNCTION PINS

analog.com

Rev. G | 33 of 51

Furthermore, to make use of amplitude control, the user must be

sure to program the OSK enable bit in the CFR1 register (0x00[8])

to Logic 1.

The combination of the F[3:0] pins and Bits[31:0] provides the

AD9915 with unprecedented modulation capability by allowing the

user direct control of the DDS parameters (frequency, phase, ampli-

tude, or various combinations thereof). Furthermore, the parallel

port operates at a sample rate equal to 1/16 of the system sample

clock. This allows for updates of the DDS parameters at rates of

up to 156 MSPS (assuming a 2.5 GHz system clock) allowing the

AD9915 to accommodate applications with wideband modulation

requirements.

Be aware that the frequency, phase, and amplitude changes ap-

plied at the parallel port travel to the DDS core over different

paths, experiencing different propagation times (latency). Therefore,

modulating more than one DDS parameter necessitates setting the

device matched latency enable bit in the CFR2 register (0x01[15]),

which equalizes the latency of each DDS parameter as it propa-

gates from the parallel port to the DDS core. Note that high speed

modulation requires a DAC reconstruction filter with sufficient band-

width to accommodate the instantaneous time domain transitions.

Because direct access to the DDS parameters occurs via the FTW,

POW, and AMP registers, the IO_UPDATE pin (see Figure 41)

adds another layer of flexibility. That is, by default, 0x00[17] = 0.

Therefore, writing data to the FTW, POW, or AMP register does

not make the data immediately available to the DDS core. Instead,

the user must assert the IO_UPDATE pin to transfer the data from

the FTW, POW, and AMP registers to the DDS core. Asserting the

IO_UPDATE pin gives the user a level of control over the timing

of when an FTW, POW, or AMP register change is applied to the

DDS core. Note that assertion of IO_UPDATE or changing the state

of the profile select pins (PS2 to PS0) is functionally equivalent.

Furthermore, either action is gated by the rising edge of the internal

SYNC_CLK signal.

However, when the logic levels applied to the function pins (F[3:0])

= 0010 to 1101 (that is, the high speed parallel data port is active),

programming 0x00[17] = 1 activates streaming mode. In streaming

mode, data at the D[31:0] pins is transferred to the FTW, POW,

or AMP register and directly to the DDS core on each rising edge

of the internal SYNC_CLK signal. Thus, streaming mode provides

for wide band modulation by eliminating the need to assert IO_UP-

DATE.

As an example to demonstrate the flexibility of the parallel data

port, suppose an application requires frequency and amplitude

modulation with full 32-bit frequency resolution and full 12-bit am-

plitude resolution. Note that none of the F[3:0] pin combinations

supports such modulation capability directly. To circumvent this

problem, program 0x00[17] = 0 (that is, disable streaming mode).

This setting allows the use of two direct mode cycles of the 32-pin

parallel port, each with a different function pin setting, without

affecting the DDS core until assertion of the IO_UPDATE pin. That

is, the first direct mode cycle constitutes setting the function pins

to F[3:0] = 0010, which routes all 32 bits to the FTW register

(frequency). The second direct mode cycle constitutes setting the

function pins to F[3:0] = 0100, which provides full 12-bit access

to the AMP register (amplitude). Be aware, however, that F[3:0] =

0100 also includes the POW register (phase). Therefore, be sure

to keep the phase bits unchanged from their previous value. Next,

toggle the IO_UPDATE pin, which synchronously (on the rising

edge of the internal SYNC_CLK signal) transfers the new frequency

and phase values from the FTW and POW registers to the DDS

core. This mode of operation reduces the overall modulation rate

by a factor of three because it requires two direct mode cycles (a

minimum of two SYNC_CLK periods) followed by an IO_UPDATE

assertion. However, this mode still allows modulation sample rates

as high as ~52 MSPS.

AD9915/PCBZ Datasheet(PDF) 33 Page - Analog Devices

AD9915/PCBZ Datasheet(HTML) 33 Page - Analog Devices

Html Pages

1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51

Datasheet Download

Link URL