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AD9915/PCBZ Datasheet(PDF) 47 Page - Analog Devices |
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AD9915/PCBZ Datasheet(HTML) 47 Page - Analog Devices |
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47 / 51 page  Data Sheet AD9915 REGISTER MAP AND BIT DESCRIPTIONS analog.com Rev. G | 47 of 51 Table 19. Bit Descriptions for CFR2 Bit(s) Mnemonic Description [7:0] Open Open. Control Function Register 3 (CFR3)—Address 0x02 Table 20. Bit Descriptions for CFR3 Bit(s) Mnemonic Description [31:23] Open Open. 22 PLL input divider reset 0 = disables PLL input divider reset function. 1 = resets the PLL input divider. [21:20] PLL input divide value Divides the input REF CLK signal to the PLL by one of three values (12, 4, 8). Bit 17 must be set to Logic 1 to use the PLL input divider. 00 = disable divider 01 = divide by 2 10 = divide by 4 11 = divide by 8 19 PLL input doubler select 0 = selects the feedthrough path. 1 = selects the 2× path. This bit is only meaningful when CFR3[18] = 1 and CFR3[17] = 0. 18 PLL enable 0 = disables the internal PLL. 1 = the internal PLL is enabled and the output generates the system clock. The PLL must be calibrated when enabled via VCO calibration in Register CFR1, Bit 24. 17 PLL input divider select 0 = selects the feed through and 2× multiplier paths. 1 = selects the PLL input divider path. This bit is only meaningful when CFR3[18] = 1. 16 PLL edge select 0 = select rising edge. 1 = select falling edge. This bit is only meaningful when CFR3[18] = 1, CFR3[17] = 0 and CFR3[19] = 0. The PLL locks to the selected edge of REF_CLK. [15:8] Feedback divider N The N divider value in Bits[15:8] is one part of the total PLL multiplication available. The second part is the fixed divide by two element in the feedback path. Therefore, the total PLL multiplication value is 2N. The valid N divider range is 10× to 255×. The default N value for Bits[15:8] = 25, which sets the total default PLL multiplication to 50× or 2N. 7 Open Open. 6 Manual ICP selection 0 = the internal charge pump current is chosen automatically during the VCO calibration routine (default). 1 = the internal charge pump is set manually per Table 7. [5:3] ICP Manual charge pump current selection. See Table 7. 2 Lock detect enable 0 = disables PLL lock detection. 1 = enables PLL lock detection. [1:0] Minimum LDW Selects the number of REF CLK cycles that the phase error (at the PFD inputs) must remain within before a PLL lock condition can be read back via Bit 24 in Register 0x00. 00 = 128 REF CLK cycles 01 = 256 REF CLK cycles 10 = 512 REF CLK cycles 11 = 1024 REF CLK cycles Control Function Register 4 (CFR4)—Address 0x03 Table 21. Bit Descriptions for DAC Bit(s) Mnemonic Description [31:27] Open Open. |
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