AD9915SLASHPCBZ datasheet(22/51 Pages) AD

22 / 51 page

Data Sheet

AD9915

FUNCTIONAL BLOCK DETAIL

analog.com

Rev. G | 22 of 51

CLOCK INPUT (REF_CLK/REF_CLK)

REF_CLK/REF_CLK Overview

The AD9915 supports a number of options for producing the

internal SYSCLK signal (that is, the DAC sample clock) via the

REF_CLK/REF_CLK input pins. The REF_CLK input can be driv-

en directly from a differential or single-ended source. There is

also an internal phase-locked loop (PLL) multiplier that can be

independently enabled. However, the PLL limits the SYSCLK signal

between 2.4 GHz and 2.5 GHz operation. A differential signal is

recommended when the PLL is bypassed. A block diagram of the

REF_CLK functionality is shown in Figure 32. Figure 32 also shows

how the CFR3 control bits are associated with specific functional

blocks.

Figure 32. REF_CLK Block Diagram

The PLL enable bit (0x02[18]) chooses between the PLL path and

the direct input path. The direct input path is the default condition.

When the direct input path is selected, the REF_CLK/REF_CLK

pins must be driven by an external signal source (single-ended or

differential). Input frequencies up to 2.5 GHz are supported.

Direct Driven REF_CLK/REF_CLK

With a differential signal source, the REF_CLK/REF_CLK pins are

driven with complementary signals and ac-coupled with 0.1 µF ca-

pacitors. With a single-ended signal source, either a single-ended-

to-differential conversion can be employed or the REF_CLK input

can be driven single-ended directly. In either case, 0.1 µF capaci-

tors ac couple both REF_CLK/REF_CLK pins to avoid disturbing

the 2 V dc internal bias voltage. See Figure 33 for more details.

The REF_CLK/REF_CLK input resistance is ~2.5 kΩ differential

(~1.2 kΩ single-ended). Most signal sources have relatively low

output impedances. The REF_CLK/REF_CLK input resistance is

relatively high; therefore, the effect on the termination impedance is

negligible and can usually be chosen to be the same as the output

impedance of the signal source. The bottom two examples in Figure

33 assume a signal source with a 50 Ω output impedance.

Figure 33. Direct Connection Diagram

Phase-Locked Loop (PLL) Multiplier

An internal PLL provides the option to use a reference clock fre-

quency that is significantly lower than the system clock frequency.

The PLL supports a wide range of even programmable frequency

multiplication factors (20× to 510×; that is, two times the program-

med value of N (CFR3[15:8])) as well as a programmable charge

pump current and external loop filter components (connected via

the PLL LOOP_FILTER pin). These features add an extra layer of

flexibility to the PLL, allowing optimization of phase noise perform-

ance and flexibility in frequency plan development. The PLL is also

equipped with a lock detector, enabled via CFR3[2] = 1. When

enabled, lock detect status is available via 0x1B[24].

The PLL output frequency range (fSYSCLK) is constrained to the

range of 2.4 GHz ≤ fSYSCLK ≤ 2.5 GHz by the internal VCO.

As shown in Figure 32, to use the PLL, the user must program

CFR3[18] = 1, which enables the PLL circuitry and selects the VCO

output of the PLL as the internal system clock (SYSCLK) source.

There are three ways to route the REF_CLK input signal to the

input of the PLL, as follows:

►

Feedthrough (PLL input frequency = REF_CLK input frequency)

►

Divided (PLL input frequency = REF_CLK input frequency divid-

ed by 2, 4, or 8)

►

Multiplied (PLL input frequency = twice the REF_CLK input

frequency)

Regardless of the routing option chosen, the user must ensure the

frequency at the input to the PLL does not exceed 125 MHz.

The feedthrough path is the default PLL input option (in effect

when CFR3[17] = 0 and CFR3[19] = 0). Because the feedthrough

path delivers the REF_CLK input signal to the PLL input without

frequency division or multiplication, the PLL can be made to align

with either the rising or falling edge of the REF_CLK input signal

via CFR3[16]. Logic 0 selects the rising edge of the REF_CLK input

signal, whereas Logic 1 selects the falling edge. Normally, there

is no particular advantage over choosing one edge over the other.

However, some clock sources exhibit more jitter on one edge than

AD9915/PCBZ Datasheet(PDF) 22 Page - Analog Devices

AD9915/PCBZ Datasheet(HTML) 22 Page - Analog Devices

Html Pages

1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51

Datasheet Download

Link URL