AD9915SLASHPCBZ datasheet(23/51 Pages) AD

23 / 51 page

Data Sheet

AD9915

FUNCTIONAL BLOCK DETAIL

analog.com

Rev. G | 23 of 51

the other. Thus, the ability to choose the edge with less jitter yields

less noise.

The divided path is in effect when CFR3[17] = 1 (the state of

CFR3[16] and CFR3[19] is immaterial). The user has four options

via CFR3[21:20]: disable the divider or divide by 2, 4, or 8. Note

that the divided path uses the inverted version of the REF_CLK

input signal exclusively.

The multiplied path is in effect when CFR3[19] = 1 and CFR3[17]

= 0, which doubles the frequency of the REF_CLK input before

delivering it to the input of the PLL.

VCO Calibration

When using the PLL to generate the system clock, VCO calibration

is required to tune the VCO appropriately and achieve good per-

formance. When the reference input signal is stable, the VCO cal

enable bit in the CFR1 register, 0x00[24], must be asserted. Sub-

sequent VCO calibrations require that the VCO calibration bit be

cleared prior to initiating another VCO calibration. VCO calibration

must occur before DAC calibration to ensure optimal performance

and functionality.

PLL Charge Pump/Total Feedback Divider

The charge pump current (ICP) value is automatically chosen via

the VCO calibration process and N value (N = 10 to 255) stored

in Feedback Divider N[7:0] in the CFR3 Register (0x02[15:8]). N

values below 10 must be avoided.

Note that the total PLL multiplication value for the PLL is always 2N

due to the fixed divide by 2 element in the feedback path. This is

shown in Figure 34. The fixed divide by 2 element forces only even

PLL multiplication.

To manually override the charge pump current value, the manual

ICP selection bit in CFR3 (0x02[6]) must be set to Logic 1.This

provides the user with additional flexibility to optimize the PLL

performance. Table 7 lists the bit settings vs. the nominal charge

pump current.

Table 7. PLL Charge Pump Current

ICP Bits (CFR3[5:3])

Charge Pump Current, ICP (μA)

000

125

001

250

010

375

011

500 (default)

100

625

101

750

110

875

111

1000

Table 8. N Divider vs. Charge Pump Current

N Divider Range

Recommended Charge Pump Current, ICP (μA)

10 to 15

125

Table 8. N Divider vs. Charge Pump Current

N Divider Range

Recommended Charge Pump Current, ICP (μA)

16 to 23

250

24 to 35

375

36 to 43

500

44 to 55

625

56 to 63

750

64 to 79

875

80 to 100

1000

PLL Loop Filter Components

The loop filter is mostly internal to the device, as shown in Figure

34. The recommended external capacitor value is 560 pF. Because

CP and RPZ are integrated, it is not recommended to adjust the

loop bandwidth via the external capacitor value. The better option

is to adjust the charge pump current even though it is a coarse

adjustment.

For example, suppose the PLL is manually programmed such that

ICP = 375 μA, KV = 60 MHz/V, and N = 25. This produces a loop

bandwidth of approximately 250 kHz.

Figure 34. REF CLK PLL External Loop Filter

PLL Lock Indication

When the PLL is in use and CFR3[2] = 1, the PLL lock bit

(0x1B[24]) provides an active high indication that the PLL has

locked to the REF CLK input signal.

OUTPUT SHIFT KEYING (OSK)

The OSK function (see Figure 35) allows the user to control the

output signal amplitude of the DDS. The amplitude data generated

by the OSK block has priority over any other functional block that

is programmed to deliver amplitude data to the DDS. Therefore, the

OSK data source, when enabled, overrides all other amplitude data

sources.

The operation of the OSK function is governed by two CFR1 regis-

ter bits, OSK enable (0x00[8]) and external OSK enable (0x00[9]),

the external OSK pin, the profile pins, and the 12 bits of amplitude

scale factor found in one of eight profile registers. The profile pins

select the profile register containing the desired amplitude scale

factor.

AD9915/PCBZ Datasheet(PDF) 23 Page - Analog Devices

AD9915/PCBZ Datasheet(HTML) 23 Page - Analog Devices

Html Pages

1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51

Datasheet Download

Link URL