AD9915SLASHPCBZ datasheet(35/51 Pages) AD

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Data Sheet

AD9915

SERIAL PROGRAMMING

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controls the configuration of this pin. The default is Logic 0, which

configures the SDIO pin as bidirectional.

SDO—Serial Data Out

Data is read from this pin for protocols that use separate lines

for transmitting and receiving data. When the AD9915 operates in

single bidirectional input/output mode, this pin does not output data

and is set to a high impedance state.

SYNCIO—Input/Output Reset

SYNCIO synchronizes the input/output port state machines without

affecting the contents of the addressable registers. An active high

input on the SYNCIO pin causes the current communication cycle

to abort. After SYNCIO returns low (Logic 0), another communica-

tion cycle can begin, starting with the instruction byte write.

I/O_UPDATE—Input/Output Update

The input/output update initiates the transfer of written data from

the serial or parallel input/output port buffer to active registers.

I/O_UPDATE is active on the rising edge, and the pulse width must

be greater than one SYNC_CLK period.

SERIAL INPUT/OUTPUT TIMING DIAGRAMS

Figure 42 through Figure 45 provide basic examples of the tim-

ing relationships between the various control signals of the serial

input/output port. Most of the bits in the register map are not trans-

ferred to the internal destinations until assertion of an input/output

update, which is not included in the timing diagrams that follow.

Note that the SCLK stall condition between the instruction byte

cycle and data transfer cycle in Figure 42 to Figure 45 is not

required.

MSB/LSB TRANSFERS

The AD9915 serial port can support both most significant bit (MSB)

first or least significant bit (LSB) first data formats. This functionality

is controlled by Bit 0 in CFR1 (0x00). The default format is MSB

first. If LSB first is active, all data, including the instruction byte,

must follow LSB-first convention. Note that the highest number

found in the bit range column for each register is the MSB, and the

lowest number is the LSB for that register.

Figure 42. Serial Port Write Timing, Clock Stall Low

Figure 43. 3-Wire Serial Port Read Timing, Clock Stall Low

Figure 44. Serial Port Write Timing, Clock Stall High

Figure 45. 2-Wire Serial Port Read Timing, Clock Stall High

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