M68HC08 datasheet(218/288 Pages) FREESCALE

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Sync Processor

Data Sheet

MC68HC908BD48 — Rev. 2.1

218

Sync Processor

Freescale Semiconductor

VEDGE — VSync Interrupt Edge Select

This bit specifies the triggering edge of Vsync interrupt. When it is "0",

the rising edge of internal Vsync signal which is either from the

VSYNC pin or extracted from the composite input signal will set VSIF

flag. When it is "1", the falling edge of internal Vsync signal will set

VSIF flag. Reset clears this bit.

1 = VSIF bit will be set by rising edge of Vsync

0 = VSIF bit will be set by falling edge of Vsync

VSIF — VSync Interrupt Flag

This flag is only set by the specified edge of the internal Vsync signal,

which is either from the VSYNC input pin or extracted from the

composite sync input signal. The triggering edge is specified by the

VEDGE bit. VSIF generates an interrupt request to the CPU if the

VSIE bit is also set. This bit is cleared by writing a "0" to it or by a reset.

1 = A valid edge is detected on the Vsync

0 = No valid Vsync is detected

COMP — Composite Sync Input Enable

This bit is set to enable the separator circuit which extracts the Vsync

pulse from the composite sync input on HSYNC or SOG pin (select by

SOGSEL bit). The extracted Vsync signal is used as it were from the

VSYNC input. Reset clears this bit.

1 = Composite Sync Input Enabled

0 = Composite Sync Input Disabled

VINVO —þVSYNCO Signal Polarity

This bit, together with the ATPOL bit in SPCR1 controls the output

polarity of the VSYNCO signal (see Table 16-5).

HINVO — HSYNCO Signal Polarity

This bit, together with the ATPOL bit in SPCR1 controls the output

polarity of the HSYNCO signal (see Table 16-5).

M68HC08 Datasheet(PDF) 218 Page - Freescale Semiconductor, Inc