M68HC08 datasheet(217/288 Pages) FREESCALE

217 / 288 page

Sync Processor

MC68HC908BD48 — Rev. 2.1

Data Sheet

Freescale Semiconductor

Sync Processor

217

16.5.5 Low Vertical Frequency Detect

Logic monitors the value of the Vsync Frequency Register (VFR), and

sets the low vertical frequency flag (LVSIF) when the value of VFR is

higher than $C00 (frequency below 40.7Hz). LVSIF bit can generate an

interrupt request to the CPU when the LVSIE bit is set and I-bit in the

Condition Code Register is "0". The LVSIF bit can help the system to

detect video off mode fast.

16.6 Registers

Eight registers are associated with the Sync Processor, they outlined in

the following sections.

16.6.1 Sync Processor Control & Status Register (SPCSR)

VSIE — VSync Interrupt Enable

When this bit is set, the VSIF flag is enabled to generate an interrupt

request to the CPU. When VSIE is cleared, the VSIF flag is prevented

from generating an interrupt request to the CPU. Reset clears this bit.

1 = VSIF bit set will generate interrupt request to CPU

0 = VSIF bit set does not generate interrupt request to CPU

Address:

$0040

Bit 7

654321

Bit 0

Read:

VSIE

VEDGE

VSIF

COMP

VINVO

HINVO

VPOL

HPOL

Write:

Reset:

00000000

= Unimplemented

Figure 16-3. Sync Processor Control & Status Register (SPCSR)

M68HC08 Datasheet(PDF) 217 Page - Freescale Semiconductor, Inc

M68HC08 Datasheet(HTML) 217 Page - Freescale Semiconductor, Inc

Html Pages

1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60 61 62 63 64 65 66 67 68 69 70 71 72 73 74 75 76 77 78 79 80 81 82 83 84 85 86 87 88 89 90 91 92 93 94 95 96 97 98 99 100 ...More

Datasheet Download

Link URL