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AM29243EH Datasheet(PDF) 22 Page - Advanced Micro Devices

Part # AM29243EH
Description  Enhanced High-Performance RISC Microcontrollers
PDF  36 Pages
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Manufacturer  AMD [Advanced Micro Devices]
Direct Link  http://www.amd.com
Logo AMD - Advanced Micro Devices

AM29243EH Datasheet(HTML) 22 Page - Advanced Micro Devices

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P R E L I M I N A R Y
22
Am29240 EH Microcontroller Series
™
SWITCHING CHARACTERISTICS over COMMERCIAL Operating Ranges
Preliminary
16 MHz
20 MHz
25 MHz
No.
Parameter Description
Test Conditions 1
Min
Max
Min
Max
Min
Max
Unit
1
INCLK Period (=0.5T)
30
50
25
50
20
50
ns
2
INCLK High Time
10
8
6
ns
3
INCLK Low Time
10
8
6
ns
4
INCLK Rise Time
0
5
0
5
0
5
ns
5
INCLK Fall Time
0
5
0
5
0
5
ns
6
MEMCLK Delay from INCLK
Note 1C, 3
1
7
1
7
1
7
ns
8
MEMCLK High Time
Note 1C
0.5T–3
0.5T–3
0.5T–3
ns
9
MEMCLK Low Time
Note 1C
0.5T–3
0.5T–3
0.5T–3
ns
10
MEMCLK Rise Time
Note 1C
1
4
1
4
1
4
ns
11
MEMCLK Fall Time
Note 1C
1
4
1
4
1
4
ns
12a
Synchronous Output Valid Delay from MEMCLK Rising Edge
PIO15–PIO0, STAT2–STAT0,
PIACS5–PIACS0, and
RAS3–RAS0
Note 1A
1
13
1
12
1
11
ns
CAS3–CAS0 Rising Edge/
CAS3–CAS0 Falling Edge
Notes 1B, 4B
1
17/11
1
15/9
1
13/7
ns
All others
Note 1B
1
12
1
11
1
10
ns
12b
Synchronous Output Valid Delay from MEMCLK Falling Edge
PIO15–PIO0, STAT2–STAT0,
PIACS5–PIACS0
Note 1A
1
12
1
11
1
10
ns
RAS3–RAS0
Note 1B
1
15
1
14
1
13
ns
CAS3–CAS0 Falling Edge
Notes 1B, 4B
1
11
1
9
1
7
ns
All others
Note 1B
1
11
1
10
1
9
ns
13
Synchronous Output Disable
Delay from MEMCLK Rising
Edge
1
12
1
11
1
10
ns
14
Synchronous Input Setup Time to MEMCLK Rising Edge
ID31–ID0 and IDP3–IDP0 for
DRAM access
Parity Enabled
Note 4A
18
16
15
ns
ID31–ID0 for DRAM access
Parity Disabled
Note 4A
10
8
7
ns
All others
10
8
7
ns
15
Available CAS Access Time
(TCAS–TSetup)
Note 4B
25
24
19
ns
16a
Synchronous Input Hold Time to
MEMCLK Rising Edge
Note 4A
0
0
0
ns
16b
Synchronous Input Hold Time to
CAS Rising Edge
Note 4B
3
3
3
ns



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