3823 datasheet(59/76 Pages) RENESAS

59 / 76 page

Rev.2.02

Jun 19, 2007

page 59 of 73

REJ03B0146-0202

3823 Group

NOTES ON PROGRAMMING

Processor Status Register

The contents of the processor status register (PS) after a reset are

undefined, except for the interrupt disable flag (I) which is “1”. Af-

ter a reset, initialize flags which affect program execution.

In particular, it is essential to initialize the index X mode (T) and

the decimal mode (D) flags because of their effect on calculations.

Initialize these flags at the beginning of the program.

Interrupt

The contents of the interrupt request bits do not change immedi-

ately after they have been written. After writing to an interrupt

request register, execute at least one instruction before perform-

ing a BBC or BBS instruction.

Decimal Calculations

•To calculate in decimal notation, set the decimal mode flag (D)

to “1”, then execute an ADC or SBC instruction. After executing

an ADC or SBC instruction, execute at least one instruction be-

fore executing a SEC, CLC, or CLD instruction.

• In decimal mode, the values of the negative (N), overflow (V),

and zero (Z) flags are invalid.

Timers

If a value n (between 0 and 255) is written to a timer latch, the fre-

quency division ratio is 1/(n + 1).

Multiplication and Division Instructions

The index mode (T) and the decimal mode (D) flags do not affect

the MUL and DIV instruction.

The execution of these instructions does not change the contents

of the processor status register.

Ports

The contents of the port direction registers cannot be read.

The following cannot be used:

• The data transfer instruction (LDA, etc.)

• The operation instruction when the index X mode flag (T) is “1”

• The addressing mode which uses the value of a direction regis-

ter as an index

• The bit-test instruction (BBC or BBS, etc.) to a direction register

• The read-modify-write instruction (ROR, CLB, or SEB, etc.) to a

direction register

Use instructions such as LDM and STA, etc., to set the port direc-

tion registers.

Serial Interface

In clock synchronous serial I/O, if the receive side is using an ex-

ternal clock and it is to output the SRDY signal, set the transmit

enable bit, the receive enable bit, and the SRDY output enable bit

to “1”.

Serial I/O continues to output the final bit from the TXD pin after

transmission is completed.

A/D Converter

The comparator is constructed linked to a capacitor. The conver-

sion accuracy may be low because the charge is lost if the

conversion speed is not enough. Accordingly, set f(XIN) to at least

500kHz during A/D conversion in the middle-or high-speed mode.

Also, do not execute the STP or WIT instruction during an A/D

conversion.

In the low-speed mode, since the A/D conversion is executed by

the on-chip oscillator, the minimum value of f(XIN) frequency is not

limited.

LCD Drive Control Circuit

Execution of the STP instruction sets the LCD enable bit (bit 3 of

the LCD mode register) to “0” and the LCD panel turns off.To

make the LCD panel turn on after returning from the stop mode,

set the LCD enable bit to “1”.

Instruction Execution Time

The instruction execution time is obtained by multiplying the fre-

quency of the internal clock φ by the number of cycles needed to

execute an instruction.

The number of cycles required to execute an instruction is shown

in the list of machine instructions.

The frequency of the internal clock φ is half of the XIN frequency.

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