3823 datasheet(13/76 Pages) RENESAS

13 / 76 page

Rev.2.02

Jun 19, 2007

page 13 of 73

REJ03B0146-0202

3823 Group

[CPU Mode Register (CPUM)] 003B16

The CPU mode register contains the stack page selection bit and

the internal system clock selection bit.

The CPU mode register is allocated at address 003B16.

Fig. 8 Structure of CPU mode register

Not available

Processor mode bits

b1 b0

0 : Single-chip mode

1 :

0 :

1 :

Stack page selection bit

0 : 0 page

1 : 1 page

Not used (returns “1” when read)

(Do not write “0” to this bit)

Port XC switch bit (Note 1)

0 : I/O port function (stop oscillating)

1 : XCIN–XCOUT oscillating function

Main clock (XIN–XOUT) stop bit (Note 2)

0 : Oscillating

1 : Stopped

Main clock division ratio selection bit

0 : f(XIN)/2 (frequency/2 mode), or f(XIN)/4 (frequency/4 mode) (Note 3)

1 : f(XIN)/8 (frequency/8 mode)

Internal system clock selection bit

0 : XIN–XOUT selected (frequency/2/4/8 mode)

1 : XCIN–XCOUT, or on-chip oscillator selected (low-speed mode) (Note 4)

CPU mode register

(CPUM (CM) : address 003B16)

Note 1: In low speed mode (XCIN is selected as the system clock φ), XCIN-XCOUT oscillation does not stop even if the port XC

switch bit is set to "0".

2: In frequency/2/4/8 mode, XIN-XOUT oscillation does not stop even if the main clock (XIN-XOUT) stop bit is set to "1".

3: When the system clock φ is divided by 4 of f(XIN), set the bit 6 in the CPU mode register to “0” after setting the bit 1

in the CPU mode extension register to “1”.

4: When using the on-chip oscillator in low-speed mode, set the bit 7 in the CPU mode register to “1” after setting the

bit 0 in the CPU mode extension register to “1”.

[CPU Mode Extension Register (EXPCM)] 002B16

f(XIN) divided by 4 for the system clock f and the on-chip oscillator

for the system clock f in low-speed mode can be selected by set-

ting the CPU mode extension register. When the system clock f is

divided by 4 of f(XIN), set the bit 6 in the CPU mode register to “0”

after setting the bit 1 in the CPU mode extension register to “1”.

When using the on-chip oscillator in low-speed mode, set the bit 7

in the CPU mode register to “1” after setting the bit 0 in the CPU

mode extension register to “1”.

Fig. 9 Structure of CPU mode extension register

On-chip oscillator control bit

0 : On-chip oscillator not used

(On -chip oscillator sotpping)

1 : On-chip oscillator used (Note 1)

(On -chip oscillator oscillating)

Frequency/4 mode control bit (Note 2)

0 : Frequency/2 mode φ = f(XIN)/2

1 : Frequency/4 mode φ = f(XIN)/4

Not used (returns “0” when read)

(Do not write “1” to this bit)

CPU mode extension register

(EXPCM : address 002B16)

1 : The on-chip oscillator is selected for the operation clock in low-speed mod regardless

of XCIN-XCOUT.

2 : Valid only when the main clock division ratio selection bit (bit 6 in the CPU mode

When "1" (frequency/8 mode) is selected for the main clock division ratio selection bit or

when the internal system clock selection bit is set to 1, set "0" to the frequency/4 mode

control bit.

Note

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