TDA9964 datasheet(7/24 Pages) PHILIPS

7 / 24 page

2000 May 02

Philips Semiconductors

Objective speciﬁcation

12-bit, 3.0 V, 30 Msps analog-to-digital

interface for CCD cameras

TDA9964

Digital inputs

PINS: SHP, SHD AND CLK (REFERENCED TO DGND)

VIL

LOW-level input voltage

−

0.6

VIH

HIGH-level input voltage

2.2

−

5.5

input current

≤ Vi ≤ 5.5 V

−3

−

µA

input impedance

fCLK =30MHz

−

Ω

input capacitance

fCLK =30MHz

−−

2pF

PINS: CLPDM, CLPOB, SEN, SCLK, SDATA, STBY, OE, BLK, VSYNC

VIL

LOW-level input voltage

−

0.6

VIH

HIGH-level input voltage

2.2

−

5.5

input current

≤ Vi ≤ 5.5 V

−2

−

µA

Clamps

GLOBAL CHARACTERISTICS OF THE CLAMP LOOPS

tW(clamp)

clamp active pulse width in

number of pixels

PGA code = 255 for

maximum 4 LSB error

−−

pixels

INPUT CLAMP (DRIVEN BY CLPDM)

gm(CDS)

CDS input clamp

transconductance

−

Correlated Double Sampling (CDS)

Vi(CDS)(p-p)

maximum peak-to-peak CDS

input amplitude (video signal)

VCC = 2.85 V

650

−−

VCC ≥ 3.0 V

800

−−

Vreset(max)

maximum CDS input reset

pulse amplitude

500

−−

Ii(IN)

input current into pin IN

at ﬂoating gate level

tbf

−

tbf

µA

input capacitance

−

tCDS(min)

CDS control pulses minimum

active time

Vi(CDS)(p-p) = 800 mV

black to white transition in

1 pixel with 99% Vi recovery

−

th(IN;SHP)

CDS input hold time (pin IN)

compared to control pulse

SHP

VCCA =VCCD = 3.0 V;

Tamb =25 °C;

see Figs 3 and 4

−

th(IN;SHD)

CDS input hold time (pin IN)

compared to control pulse

SHD

VCCA =VCCD = 3.0 V;

Tamb =25 °C;

see Figs 3 and 4

−

Ampliﬁer

DRPGA

PGA dynamic range

−

∆GPGA

PGA gain step

0.08

0.10

0.12

Analog-to-Digital Converter (ADC)

DNL

differential non linearity

fpix = 30 MHz; ramp input

−±0.5

±0.9

LSB

SYMBOL

PARAMETER

CONDITIONS

MIN.

TYP.

MAX.

UNIT

TDA9964 Datasheet(PDF) 7 Page - NXP Semiconductors

TDA9964 Datasheet(HTML) 7 Page - NXP Semiconductors

Html Pages

1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24

Datasheet Download

Link URL