TDA9964 datasheet(2/24 Pages) PHILIPS

2 / 24 page

2000 May 02

Philips Semiconductors

Objective speciﬁcation

12-bit, 3.0 V, 30 Msps analog-to-digital

interface for CCD cameras

TDA9964

FEATURES

• Correlated Double Sampling (CDS), Programmable

Gain Amplifier (PGA), 12-bit Analog-to-Digital

Converter (ADC) and reference regulator included

• Fully programmable via a 3-wire serial interface

• Sampling frequency up to 30 MHz

• PGA gain range of 24 dB (in steps of 0.1 dB)

• Low power consumption of only 205 mW at 2.7 V

• Power consumption in standby mode of 4.5 mW (typ.)

• 3.0 V operation and 2.5 to 3.6 V operation for the digital

outputs

• All digital inputs accept 5 V signals

• Active control pulses polarity selectable via serial

interface

• 8-bit DAC included for analog settings

• TTL compatible inputs, CMOS compatible outputs.

APPLICATIONS

• Low-power, low-voltage CCD camera systems.

GENERAL DESCRIPTION

The TDA9964 is a 12-bit analog-to-digital interface for

CCD cameras. The device includes a correlated double

sampling circuit, PGA, clamp loops and a low-power 12-bit

ADC together with its reference voltage regulator.

The PGA gain and the ADC input clamp level are

controlled via the serial interface.

An additional DAC is provided for additional system

controls; its output voltage range is 1.0 V p-p, which is

available at pin OFDOUT.

QUICK REFERENCE DATA

ORDERING INFORMATION

SYMBOL

PARAMETER

CONDITIONS

MIN. TYP. MAX. UNIT

VCCA

analog supply voltage

2.7

3.0

3.6

VCCD

digital supply voltage

2.7

3.0

3.6

VCCO

digital outputs supply voltage

2.5

2.7

3.6

ICCA

analog supply current

all clamps active

−

ICCD

digital supply current

−

ICCO

digital outputs supply current

fpix = 30 MHz; CL = 10 pF; input

ramp response time is 800

µs

−

ADCres

ADC resolution

−

bits

Vi(CDS)(p-p) maximum CDS input voltage (peak-to-peak

value)

VCC = 2.85 V

650

−−

VCC ≥ 3.0 V

800

−−

fpix(max)

maximum pixel frequency

−−

MHz

fpix(min)

minimum pixel frequency

tbf

−−

MHz

DRPGA

PGA dynamic range

−

Ntot(rms)

total noise from CDS input to ADC output

PGA gain = 0 dB; see Fig.8

−

1.5

−

LSB

Ein(rms)

equivalent input noise (RMS value)

gain = 24 dB

−

−µV

Ptot

total power consumption

VCCA =VCCD =VCCO =3V

−

230

−

VCCA =VCCD =VCCO = 2.7 V

−

205

−

TYPE NUMBER

PACKAGE

NAME

DESCRIPTION

VERSION

TDA9964HL

LQFP48

plastic low proﬁle quad ﬂat package; 48 leads; body 7

× 7 × 1.4 mm

SOT313-2

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