DS2755: High-Accuracy Battery Fuel Gauge with Snapshot

11 of 20

rising edge of the DQ high to low to high pulse. The Snapshot mode can be abandoned by sending a 1-Wire Reset

instead of the synchronization pulse. The rising edge DQ trigger is formed by the first data bit after issuing the Sync

Function command. A full byte can be issued, but the rising edge of the first bit sets the trigger point. [[The SNAP

bit is set after the rising edge trigger: timing is not critical and could be several 100

μs later since it cannot be read

quickly via 1-Wire]]. If a 1-wire reset is issued instead of a data bit, then the Snapshot is abandoned (SNAP bit not

set).]

The Snapshot Synchronization Timing in Figure 10 illustrates the timing of the Snapshot current and voltage

sample apertures relative to the DQ rising edge trigger and one timeslot GSM power amp load pulse. In the

within a single GSM timeslot.

Figure 10. SNAPSHOT SYNCHRONIZATION TIMING

MEMORY

The DS2755 has a 256-byte linear address space with registers for instrumentation, status, and control in the lower

32 bytes, with lockable EEPROM and SRAM memory occupying portions of the remaining address space. All

EEPROM and SRAM memory is general-purpose except addresses 31h and 33h, which should be written with the

default values for the Status Register and Accumulation Bias Register, respectively. When the MSB of any two-

byte register is read, the MSB and LSB values are latched and held for the duration of the Read Data command.

This prevents updates during the read to ensure synchronization between the two register bytes. For consistent

results, always read the MSB and the LSB of a two-byte register during the same Read Data command sequence.

In describing register control and status bits, the terms set and clear refer to internal operations which manipulate

bit values. The terms read and write refer to 1-Wire access to the bit values. Several bits are set internally but

require the host system to write them to a 0 value.

EEPROM memory is shadowed by RAM to eliminate programming delays between writes and to allow the data to

be verified by the host system before being copied to EEPROM. The Read Data and Write Data protocols to/from

EEPROM memory addresses access the shadow RAM. The Recall Data function command transfers data from the

EEPROM to the shadow RAM. The Copy Data function command transfers data from the shadow RAM to the

data updates shadow RAM. In locked EEPROM blocks, the Write Data command is ignored. The Copy Data

function command copies the contents of shadow RAM to EEPROM in an unlocked block of EEPROM but has no

effect on locked blocks. The Recall Data function command copies the contents of a block of EEPROM to shadow

RAM regardless of whether the block is locked or not.